444 lines
8.0 KiB
ArmAsm
444 lines
8.0 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file contains assembly-language implementations
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* of IP-style 1's complement checksum routines.
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Severely hacked about by Paul Mackerras (paulus@cs.anu.edu.au).
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*/
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#include <linux/sys.h>
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#include <asm/processor.h>
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#include <asm/errno.h>
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#include <asm/ppc_asm.h>
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#include <asm/export.h>
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/*
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* Computes the checksum of a memory block at buff, length len,
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* and adds in "sum" (32-bit).
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*
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* __csum_partial(r3=buff, r4=len, r5=sum)
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*/
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_GLOBAL(__csum_partial)
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addic r0,r5,0 /* clear carry */
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srdi. r6,r4,3 /* less than 8 bytes? */
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beq .Lcsum_tail_word
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/*
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* If only halfword aligned, align to a double word. Since odd
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* aligned addresses should be rare and they would require more
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* work to calculate the correct checksum, we ignore that case
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* and take the potential slowdown of unaligned loads.
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*/
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rldicl. r6,r3,64-1,64-2 /* r6 = (r3 >> 1) & 0x3 */
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beq .Lcsum_aligned
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li r7,4
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sub r6,r7,r6
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mtctr r6
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1:
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lhz r6,0(r3) /* align to doubleword */
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subi r4,r4,2
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addi r3,r3,2
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adde r0,r0,r6
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bdnz 1b
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.Lcsum_aligned:
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/*
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* We unroll the loop such that each iteration is 64 bytes with an
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* entry and exit limb of 64 bytes, meaning a minimum size of
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* 128 bytes.
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*/
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srdi. r6,r4,7
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beq .Lcsum_tail_doublewords /* len < 128 */
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srdi r6,r4,6
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subi r6,r6,1
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mtctr r6
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stdu r1,-STACKFRAMESIZE(r1)
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std r14,STK_REG(R14)(r1)
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std r15,STK_REG(R15)(r1)
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std r16,STK_REG(R16)(r1)
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ld r6,0(r3)
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ld r9,8(r3)
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ld r10,16(r3)
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ld r11,24(r3)
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/*
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* On POWER6 and POWER7 back to back adde instructions take 2 cycles
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* because of the XER dependency. This means the fastest this loop can
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* go is 16 cycles per iteration. The scheduling of the loop below has
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* been shown to hit this on both POWER6 and POWER7.
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*/
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.align 5
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2:
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adde r0,r0,r6
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ld r12,32(r3)
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ld r14,40(r3)
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adde r0,r0,r9
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ld r15,48(r3)
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ld r16,56(r3)
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addi r3,r3,64
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adde r0,r0,r10
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adde r0,r0,r11
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adde r0,r0,r12
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adde r0,r0,r14
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adde r0,r0,r15
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ld r6,0(r3)
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ld r9,8(r3)
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adde r0,r0,r16
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ld r10,16(r3)
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ld r11,24(r3)
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bdnz 2b
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adde r0,r0,r6
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ld r12,32(r3)
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ld r14,40(r3)
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adde r0,r0,r9
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ld r15,48(r3)
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ld r16,56(r3)
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addi r3,r3,64
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adde r0,r0,r10
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adde r0,r0,r11
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adde r0,r0,r12
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adde r0,r0,r14
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adde r0,r0,r15
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adde r0,r0,r16
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ld r14,STK_REG(R14)(r1)
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ld r15,STK_REG(R15)(r1)
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ld r16,STK_REG(R16)(r1)
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addi r1,r1,STACKFRAMESIZE
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andi. r4,r4,63
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.Lcsum_tail_doublewords: /* Up to 127 bytes to go */
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srdi. r6,r4,3
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beq .Lcsum_tail_word
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mtctr r6
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3:
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ld r6,0(r3)
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addi r3,r3,8
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adde r0,r0,r6
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bdnz 3b
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andi. r4,r4,7
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.Lcsum_tail_word: /* Up to 7 bytes to go */
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srdi. r6,r4,2
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beq .Lcsum_tail_halfword
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lwz r6,0(r3)
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addi r3,r3,4
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adde r0,r0,r6
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subi r4,r4,4
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.Lcsum_tail_halfword: /* Up to 3 bytes to go */
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srdi. r6,r4,1
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beq .Lcsum_tail_byte
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lhz r6,0(r3)
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addi r3,r3,2
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adde r0,r0,r6
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subi r4,r4,2
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.Lcsum_tail_byte: /* Up to 1 byte to go */
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andi. r6,r4,1
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beq .Lcsum_finish
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lbz r6,0(r3)
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#ifdef __BIG_ENDIAN__
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sldi r9,r6,8 /* Pad the byte out to 16 bits */
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adde r0,r0,r9
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#else
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adde r0,r0,r6
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#endif
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.Lcsum_finish:
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addze r0,r0 /* add in final carry */
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rldicl r4,r0,32,0 /* fold two 32 bit halves together */
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add r3,r4,r0
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srdi r3,r3,32
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blr
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EXPORT_SYMBOL(__csum_partial)
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.macro srcnr
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100:
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EX_TABLE(100b,.Lerror_nr)
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.endm
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.macro source
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150:
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EX_TABLE(150b,.Lerror)
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.endm
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.macro dstnr
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200:
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EX_TABLE(200b,.Lerror_nr)
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.endm
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.macro dest
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250:
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EX_TABLE(250b,.Lerror)
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.endm
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/*
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* Computes the checksum of a memory block at src, length len,
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* and adds in 0xffffffff (32-bit), while copying the block to dst.
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* If an access exception occurs, it returns 0.
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*
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* csum_partial_copy_generic(r3=src, r4=dst, r5=len)
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*/
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_GLOBAL(csum_partial_copy_generic)
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li r6,-1
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addic r0,r6,0 /* clear carry */
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srdi. r6,r5,3 /* less than 8 bytes? */
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beq .Lcopy_tail_word
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/*
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* If only halfword aligned, align to a double word. Since odd
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* aligned addresses should be rare and they would require more
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* work to calculate the correct checksum, we ignore that case
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* and take the potential slowdown of unaligned loads.
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*
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* If the source and destination are relatively unaligned we only
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* align the source. This keeps things simple.
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*/
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rldicl. r6,r3,64-1,64-2 /* r6 = (r3 >> 1) & 0x3 */
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beq .Lcopy_aligned
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li r9,4
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sub r6,r9,r6
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mtctr r6
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1:
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srcnr; lhz r6,0(r3) /* align to doubleword */
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subi r5,r5,2
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addi r3,r3,2
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adde r0,r0,r6
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dstnr; sth r6,0(r4)
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addi r4,r4,2
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bdnz 1b
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.Lcopy_aligned:
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/*
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* We unroll the loop such that each iteration is 64 bytes with an
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* entry and exit limb of 64 bytes, meaning a minimum size of
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* 128 bytes.
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*/
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srdi. r6,r5,7
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beq .Lcopy_tail_doublewords /* len < 128 */
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srdi r6,r5,6
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subi r6,r6,1
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mtctr r6
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stdu r1,-STACKFRAMESIZE(r1)
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std r14,STK_REG(R14)(r1)
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std r15,STK_REG(R15)(r1)
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std r16,STK_REG(R16)(r1)
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source; ld r6,0(r3)
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source; ld r9,8(r3)
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source; ld r10,16(r3)
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source; ld r11,24(r3)
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/*
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* On POWER6 and POWER7 back to back adde instructions take 2 cycles
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* because of the XER dependency. This means the fastest this loop can
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* go is 16 cycles per iteration. The scheduling of the loop below has
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* been shown to hit this on both POWER6 and POWER7.
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*/
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.align 5
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2:
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adde r0,r0,r6
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source; ld r12,32(r3)
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source; ld r14,40(r3)
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adde r0,r0,r9
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source; ld r15,48(r3)
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source; ld r16,56(r3)
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addi r3,r3,64
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adde r0,r0,r10
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dest; std r6,0(r4)
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dest; std r9,8(r4)
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adde r0,r0,r11
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dest; std r10,16(r4)
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dest; std r11,24(r4)
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adde r0,r0,r12
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dest; std r12,32(r4)
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dest; std r14,40(r4)
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adde r0,r0,r14
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dest; std r15,48(r4)
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dest; std r16,56(r4)
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addi r4,r4,64
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adde r0,r0,r15
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source; ld r6,0(r3)
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source; ld r9,8(r3)
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adde r0,r0,r16
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source; ld r10,16(r3)
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source; ld r11,24(r3)
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bdnz 2b
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adde r0,r0,r6
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source; ld r12,32(r3)
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source; ld r14,40(r3)
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adde r0,r0,r9
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source; ld r15,48(r3)
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source; ld r16,56(r3)
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addi r3,r3,64
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adde r0,r0,r10
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dest; std r6,0(r4)
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dest; std r9,8(r4)
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adde r0,r0,r11
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dest; std r10,16(r4)
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dest; std r11,24(r4)
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adde r0,r0,r12
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dest; std r12,32(r4)
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dest; std r14,40(r4)
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adde r0,r0,r14
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dest; std r15,48(r4)
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dest; std r16,56(r4)
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addi r4,r4,64
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adde r0,r0,r15
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adde r0,r0,r16
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ld r14,STK_REG(R14)(r1)
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ld r15,STK_REG(R15)(r1)
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ld r16,STK_REG(R16)(r1)
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addi r1,r1,STACKFRAMESIZE
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andi. r5,r5,63
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.Lcopy_tail_doublewords: /* Up to 127 bytes to go */
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srdi. r6,r5,3
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beq .Lcopy_tail_word
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mtctr r6
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3:
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srcnr; ld r6,0(r3)
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addi r3,r3,8
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adde r0,r0,r6
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dstnr; std r6,0(r4)
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addi r4,r4,8
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bdnz 3b
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andi. r5,r5,7
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.Lcopy_tail_word: /* Up to 7 bytes to go */
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srdi. r6,r5,2
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beq .Lcopy_tail_halfword
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srcnr; lwz r6,0(r3)
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addi r3,r3,4
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adde r0,r0,r6
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dstnr; stw r6,0(r4)
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addi r4,r4,4
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subi r5,r5,4
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.Lcopy_tail_halfword: /* Up to 3 bytes to go */
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srdi. r6,r5,1
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beq .Lcopy_tail_byte
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srcnr; lhz r6,0(r3)
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addi r3,r3,2
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adde r0,r0,r6
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dstnr; sth r6,0(r4)
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addi r4,r4,2
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subi r5,r5,2
|
||
|
|
|
||
|
|
.Lcopy_tail_byte: /* Up to 1 byte to go */
|
||
|
|
andi. r6,r5,1
|
||
|
|
beq .Lcopy_finish
|
||
|
|
|
||
|
|
srcnr; lbz r6,0(r3)
|
||
|
|
#ifdef __BIG_ENDIAN__
|
||
|
|
sldi r9,r6,8 /* Pad the byte out to 16 bits */
|
||
|
|
adde r0,r0,r9
|
||
|
|
#else
|
||
|
|
adde r0,r0,r6
|
||
|
|
#endif
|
||
|
|
dstnr; stb r6,0(r4)
|
||
|
|
|
||
|
|
.Lcopy_finish:
|
||
|
|
addze r0,r0 /* add in final carry */
|
||
|
|
rldicl r4,r0,32,0 /* fold two 32 bit halves together */
|
||
|
|
add r3,r4,r0
|
||
|
|
srdi r3,r3,32
|
||
|
|
blr
|
||
|
|
|
||
|
|
.Lerror:
|
||
|
|
ld r14,STK_REG(R14)(r1)
|
||
|
|
ld r15,STK_REG(R15)(r1)
|
||
|
|
ld r16,STK_REG(R16)(r1)
|
||
|
|
addi r1,r1,STACKFRAMESIZE
|
||
|
|
.Lerror_nr:
|
||
|
|
li r3,0
|
||
|
|
blr
|
||
|
|
|
||
|
|
EXPORT_SYMBOL(csum_partial_copy_generic)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
|
||
|
|
* const struct in6_addr *daddr,
|
||
|
|
* __u32 len, __u8 proto, __wsum sum)
|
||
|
|
*/
|
||
|
|
|
||
|
|
_GLOBAL(csum_ipv6_magic)
|
||
|
|
ld r8, 0(r3)
|
||
|
|
ld r9, 8(r3)
|
||
|
|
add r5, r5, r6
|
||
|
|
addc r0, r8, r9
|
||
|
|
ld r10, 0(r4)
|
||
|
|
ld r11, 8(r4)
|
||
|
|
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||
|
|
rotldi r5, r5, 8
|
||
|
|
#endif
|
||
|
|
adde r0, r0, r10
|
||
|
|
add r5, r5, r7
|
||
|
|
adde r0, r0, r11
|
||
|
|
adde r0, r0, r5
|
||
|
|
addze r0, r0
|
||
|
|
rotldi r3, r0, 32 /* fold two 32 bit halves together */
|
||
|
|
add r3, r0, r3
|
||
|
|
srdi r0, r3, 32
|
||
|
|
rotlwi r3, r0, 16 /* fold two 16 bit halves together */
|
||
|
|
add r3, r0, r3
|
||
|
|
not r3, r3
|
||
|
|
rlwinm r3, r3, 16, 16, 31
|
||
|
|
blr
|
||
|
|
EXPORT_SYMBOL(csum_ipv6_magic)
|