182 lines
4.2 KiB
C
182 lines
4.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* spu_save.c
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*
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* (C) Copyright IBM Corp. 2005
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*
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* SPU-side context save sequence outlined in
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* Synergistic Processor Element Book IV
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*
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* Author: Mark Nutter <mnutter@us.ibm.com>
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*/
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#ifndef LS_SIZE
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#define LS_SIZE 0x40000 /* 256K (in bytes) */
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#endif
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typedef unsigned int u32;
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typedef unsigned long long u64;
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#include <spu_intrinsics.h>
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#include <asm/spu_csa.h>
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#include "spu_utils.h"
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static inline void save_event_mask(void)
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{
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unsigned int offset;
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/* Save, Step 2:
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* Read the SPU_RdEventMsk channel and save to the LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(event_mask);
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regs_spill[offset].slot[0] = spu_readch(SPU_RdEventMask);
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}
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static inline void save_tag_mask(void)
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{
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unsigned int offset;
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/* Save, Step 3:
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* Read the SPU_RdTagMsk channel and save to the LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(tag_mask);
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regs_spill[offset].slot[0] = spu_readch(MFC_RdTagMask);
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}
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static inline void save_upper_240kb(addr64 lscsa_ea)
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{
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unsigned int ls = 16384;
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unsigned int list = (unsigned int)&dma_list[0];
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unsigned int size = sizeof(dma_list);
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unsigned int tag_id = 0;
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unsigned int cmd = 0x24; /* PUTL */
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/* Save, Step 7:
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* Enqueue the PUTL command (tag 0) to the MFC SPU command
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* queue to transfer the remaining 240 kb of LS to CSA.
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*/
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spu_writech(MFC_LSA, ls);
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spu_writech(MFC_EAH, lscsa_ea.ui[0]);
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spu_writech(MFC_EAL, list);
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spu_writech(MFC_Size, size);
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spu_writech(MFC_TagID, tag_id);
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spu_writech(MFC_Cmd, cmd);
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}
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static inline void save_fpcr(void)
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{
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// vector unsigned int fpcr;
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unsigned int offset;
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/* Save, Step 9:
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* Issue the floating-point status and control register
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* read instruction, and save to the LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(fpcr);
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regs_spill[offset].v = spu_mffpscr();
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}
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static inline void save_decr(void)
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{
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unsigned int offset;
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/* Save, Step 10:
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* Read and save the SPU_RdDec channel data to
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* the LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(decr);
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regs_spill[offset].slot[0] = spu_readch(SPU_RdDec);
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}
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static inline void save_srr0(void)
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{
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unsigned int offset;
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/* Save, Step 11:
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* Read and save the SPU_WSRR0 channel data to
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* the LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(srr0);
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regs_spill[offset].slot[0] = spu_readch(SPU_RdSRR0);
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}
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static inline void spill_regs_to_mem(addr64 lscsa_ea)
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{
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unsigned int ls = (unsigned int)®s_spill[0];
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unsigned int size = sizeof(regs_spill);
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unsigned int tag_id = 0;
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unsigned int cmd = 0x20; /* PUT */
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/* Save, Step 13:
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* Enqueue a PUT command (tag 0) to send the LSCSA
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* to the CSA.
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*/
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spu_writech(MFC_LSA, ls);
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spu_writech(MFC_EAH, lscsa_ea.ui[0]);
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spu_writech(MFC_EAL, lscsa_ea.ui[1]);
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spu_writech(MFC_Size, size);
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spu_writech(MFC_TagID, tag_id);
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spu_writech(MFC_Cmd, cmd);
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}
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static inline void enqueue_sync(addr64 lscsa_ea)
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{
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unsigned int tag_id = 0;
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unsigned int cmd = 0xCC;
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/* Save, Step 14:
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* Enqueue an MFC_SYNC command (tag 0).
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*/
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spu_writech(MFC_TagID, tag_id);
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spu_writech(MFC_Cmd, cmd);
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}
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static inline void save_complete(void)
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{
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/* Save, Step 18:
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* Issue a stop-and-signal instruction indicating
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* "save complete". Note: This function will not
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* return!!
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*/
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spu_stop(SPU_SAVE_COMPLETE);
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}
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/**
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* main - entry point for SPU-side context save.
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*
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* This code deviates from the documented sequence as follows:
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*
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* 1. The EA for LSCSA is passed from PPE in the
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* signal notification channels.
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* 2. All 128 registers are saved by crt0.o.
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*/
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int main()
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{
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addr64 lscsa_ea;
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lscsa_ea.ui[0] = spu_readch(SPU_RdSigNotify1);
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lscsa_ea.ui[1] = spu_readch(SPU_RdSigNotify2);
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/* Step 1: done by exit(). */
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save_event_mask(); /* Step 2. */
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save_tag_mask(); /* Step 3. */
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set_event_mask(); /* Step 4. */
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set_tag_mask(); /* Step 5. */
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build_dma_list(lscsa_ea); /* Step 6. */
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save_upper_240kb(lscsa_ea); /* Step 7. */
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/* Step 8: done by exit(). */
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save_fpcr(); /* Step 9. */
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save_decr(); /* Step 10. */
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save_srr0(); /* Step 11. */
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enqueue_putllc(lscsa_ea); /* Step 12. */
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spill_regs_to_mem(lscsa_ea); /* Step 13. */
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enqueue_sync(lscsa_ea); /* Step 14. */
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set_tag_update(); /* Step 15. */
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read_tag_status(); /* Step 16. */
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read_llar_status(); /* Step 17. */
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save_complete(); /* Step 18. */
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return 0;
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}
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