304 lines
7.6 KiB
C
304 lines
7.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copied from arch/arm64/kernel/cpufeature.c
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*
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* Copyright (C) 2015 ARM Ltd.
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/bitmap.h>
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#include <linux/ctype.h>
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#include <linux/libfdt.h>
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#include <linux/log2.h>
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#include <linux/memory.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <asm/alternative.h>
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#include <asm/cacheflush.h>
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#include <asm/errata_list.h>
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#include <asm/hwcap.h>
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#include <asm/patch.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/smp.h>
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#include <asm/switch_to.h>
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#define NUM_ALPHA_EXTS ('z' - 'a' + 1)
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unsigned long elf_hwcap __read_mostly;
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/* Host ISA bitmap */
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static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
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/**
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* riscv_isa_extension_base() - Get base extension word
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*
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* @isa_bitmap: ISA bitmap to use
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* Return: base extension word as unsigned long value
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*
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* NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
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*/
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
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{
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if (!isa_bitmap)
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return riscv_isa[0];
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return isa_bitmap[0];
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}
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EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
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/**
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* __riscv_isa_extension_available() - Check whether given extension
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* is available or not
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*
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* @isa_bitmap: ISA bitmap to use
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* @bit: bit position of the desired extension
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* Return: true or false
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*
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* NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
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*/
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
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{
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const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
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if (bit >= RISCV_ISA_EXT_MAX)
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return false;
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return test_bit(bit, bmap) ? true : false;
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}
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EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
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static bool riscv_isa_extension_check(int id)
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{
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switch (id) {
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case RISCV_ISA_EXT_ZICBOM:
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if (!riscv_cbom_block_size) {
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pr_err("Zicbom detected in ISA string, but no cbom-block-size found\n");
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return false;
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} else if (!is_power_of_2(riscv_cbom_block_size)) {
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pr_err("cbom-block-size present, but is not a power-of-2\n");
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return false;
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}
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return true;
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}
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return true;
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}
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void __init riscv_fill_hwcap(void)
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{
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struct device_node *node;
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const char *isa;
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char print_str[NUM_ALPHA_EXTS + 1];
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int i, j, rc;
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unsigned long isa2hwcap[26] = {0};
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unsigned long hartid;
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isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
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isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
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isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
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isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
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isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
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isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
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elf_hwcap = 0;
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bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
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for_each_of_cpu_node(node) {
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unsigned long this_hwcap = 0;
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DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
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const char *temp;
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rc = riscv_of_processor_hartid(node, &hartid);
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if (rc < 0)
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continue;
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if (of_property_read_string(node, "riscv,isa", &isa)) {
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pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
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continue;
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}
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temp = isa;
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#if IS_ENABLED(CONFIG_32BIT)
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if (!strncmp(isa, "rv32", 4))
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isa += 4;
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#elif IS_ENABLED(CONFIG_64BIT)
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if (!strncmp(isa, "rv64", 4))
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isa += 4;
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#endif
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/* The riscv,isa DT property must start with rv64 or rv32 */
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if (temp == isa)
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continue;
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bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
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for (; *isa; ++isa) {
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const char *ext = isa++;
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const char *ext_end = isa;
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bool ext_long = false, ext_err = false;
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switch (*ext) {
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case 's':
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/**
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* Workaround for invalid single-letter 's' & 'u'(QEMU).
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* No need to set the bit in riscv_isa as 's' & 'u' are
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* not valid ISA extensions. It works until multi-letter
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* extension starting with "Su" appears.
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*/
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if (ext[-1] != '_' && ext[1] == 'u') {
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++isa;
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ext_err = true;
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break;
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}
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fallthrough;
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case 'x':
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case 'z':
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ext_long = true;
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/* Multi-letter extension must be delimited */
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for (; *isa && *isa != '_'; ++isa)
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if (unlikely(!islower(*isa)
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&& !isdigit(*isa)))
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ext_err = true;
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/* Parse backwards */
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ext_end = isa;
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if (unlikely(ext_err))
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break;
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if (!isdigit(ext_end[-1]))
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break;
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/* Skip the minor version */
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while (isdigit(*--ext_end))
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;
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if (ext_end[0] != 'p'
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|| !isdigit(ext_end[-1])) {
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/* Advance it to offset the pre-decrement */
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++ext_end;
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break;
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}
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/* Skip the major version */
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while (isdigit(*--ext_end))
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;
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++ext_end;
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break;
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default:
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if (unlikely(!islower(*ext))) {
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ext_err = true;
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break;
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}
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/* Find next extension */
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if (!isdigit(*isa))
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break;
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/* Skip the minor version */
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while (isdigit(*++isa))
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;
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if (*isa != 'p')
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break;
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if (!isdigit(*++isa)) {
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--isa;
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break;
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}
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/* Skip the major version */
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while (isdigit(*++isa))
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;
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break;
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}
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if (*isa != '_')
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--isa;
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#define SET_ISA_EXT_MAP(name, bit) \
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do { \
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if ((ext_end - ext == sizeof(name) - 1) && \
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!memcmp(ext, name, sizeof(name) - 1) && \
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riscv_isa_extension_check(bit)) \
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set_bit(bit, this_isa); \
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} while (false) \
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if (unlikely(ext_err))
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continue;
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if (!ext_long) {
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int nr = *ext - 'a';
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if (riscv_isa_extension_check(nr)) {
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this_hwcap |= isa2hwcap[nr];
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set_bit(nr, this_isa);
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}
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} else {
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/* sorted alphabetically */
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SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
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SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
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SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
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SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
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SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
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SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
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SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
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}
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#undef SET_ISA_EXT_MAP
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}
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/*
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* All "okay" hart should have same isa. Set HWCAP based on
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* common capabilities of every "okay" hart, in case they don't
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* have.
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*/
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if (elf_hwcap)
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elf_hwcap &= this_hwcap;
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else
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elf_hwcap = this_hwcap;
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if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
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bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
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else
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bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
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}
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/* We don't support systems with F but without D, so mask those out
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* here. */
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if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
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pr_info("This kernel does not support systems with F but not D\n");
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elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
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}
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memset(print_str, 0, sizeof(print_str));
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for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
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if (riscv_isa[0] & BIT_MASK(i))
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print_str[j++] = (char)('a' + i);
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pr_info("riscv: base ISA extensions %s\n", print_str);
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memset(print_str, 0, sizeof(print_str));
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for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
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if (elf_hwcap & BIT_MASK(i))
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print_str[j++] = (char)('a' + i);
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pr_info("riscv: ELF capabilities %s\n", print_str);
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}
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#ifdef CONFIG_RISCV_ALTERNATIVE
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void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
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struct alt_entry *end,
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unsigned int stage)
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{
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struct alt_entry *alt;
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void *oldptr, *altptr;
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if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
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return;
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for (alt = begin; alt < end; alt++) {
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if (alt->vendor_id != 0)
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continue;
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if (alt->errata_id >= RISCV_ISA_EXT_MAX) {
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WARN(1, "This extension id:%d is not in ISA extension list",
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alt->errata_id);
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continue;
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}
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if (!__riscv_isa_extension_available(NULL, alt->errata_id))
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continue;
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oldptr = ALT_OLD_PTR(alt);
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altptr = ALT_ALT_PTR(alt);
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mutex_lock(&text_mutex);
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patch_text_nosync(oldptr, altptr, alt->alt_len);
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riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
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mutex_unlock(&text_mutex);
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}
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}
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#endif
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