213 lines
6.1 KiB
ArmAsm
213 lines
6.1 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Hardware-accelerated CRC-32 variants for Linux on z Systems
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*
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* Use the z/Architecture Vector Extension Facility to accelerate the
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* computing of CRC-32 checksums.
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*
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* This CRC-32 implementation algorithm processes the most-significant
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* bit first (BE).
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*
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* Copyright IBM Corp. 2015
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* Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
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*/
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#include <linux/linkage.h>
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#include <asm/nospec-insn.h>
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#include <asm/vx-insn.h>
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/* Vector register range containing CRC-32 constants */
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#define CONST_R1R2 %v9
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#define CONST_R3R4 %v10
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#define CONST_R5 %v11
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#define CONST_R6 %v12
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#define CONST_RU_POLY %v13
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#define CONST_CRC_POLY %v14
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.data
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.align 8
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/*
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* The CRC-32 constant block contains reduction constants to fold and
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* process particular chunks of the input data stream in parallel.
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*
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* For the CRC-32 variants, the constants are precomputed according to
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* these definitions:
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*
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* R1 = x4*128+64 mod P(x)
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* R2 = x4*128 mod P(x)
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* R3 = x128+64 mod P(x)
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* R4 = x128 mod P(x)
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* R5 = x96 mod P(x)
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* R6 = x64 mod P(x)
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*
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* Barret reduction constant, u, is defined as floor(x**64 / P(x)).
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*
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* where P(x) is the polynomial in the normal domain and the P'(x) is the
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* polynomial in the reversed (bitreflected) domain.
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*
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* Note that the constant definitions below are extended in order to compute
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* intermediate results with a single VECTOR GALOIS FIELD MULTIPLY instruction.
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* The righmost doubleword can be 0 to prevent contribution to the result or
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* can be multiplied by 1 to perform an XOR without the need for a separate
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* VECTOR EXCLUSIVE OR instruction.
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*
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* CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
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*
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* P(x) = 0x04C11DB7
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* P'(x) = 0xEDB88320
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*/
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.Lconstants_CRC_32_BE:
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.quad 0x08833794c, 0x0e6228b11 # R1, R2
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.quad 0x0c5b9cd4c, 0x0e8a45605 # R3, R4
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.quad 0x0f200aa66, 1 << 32 # R5, x32
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.quad 0x0490d678d, 1 # R6, 1
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.quad 0x104d101df, 0 # u
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.quad 0x104C11DB7, 0 # P(x)
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.previous
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GEN_BR_THUNK %r14
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.text
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/*
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* The CRC-32 function(s) use these calling conventions:
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*
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* Parameters:
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*
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* %r2: Initial CRC value, typically ~0; and final CRC (return) value.
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* %r3: Input buffer pointer, performance might be improved if the
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* buffer is on a doubleword boundary.
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* %r4: Length of the buffer, must be 64 bytes or greater.
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*
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* Register usage:
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*
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* %r5: CRC-32 constant pool base pointer.
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* V0: Initial CRC value and intermediate constants and results.
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* V1..V4: Data for CRC computation.
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* V5..V8: Next data chunks that are fetched from the input buffer.
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*
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* V9..V14: CRC-32 constants.
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*/
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ENTRY(crc32_be_vgfm_16)
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/* Load CRC-32 constants */
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larl %r5,.Lconstants_CRC_32_BE
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VLM CONST_R1R2,CONST_CRC_POLY,0,%r5
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/* Load the initial CRC value into the leftmost word of V0. */
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VZERO %v0
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VLVGF %v0,%r2,0
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/* Load a 64-byte data chunk and XOR with CRC */
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VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
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VX %v1,%v0,%v1 /* V1 ^= CRC */
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aghi %r3,64 /* BUF = BUF + 64 */
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aghi %r4,-64 /* LEN = LEN - 64 */
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/* Check remaining buffer size and jump to proper folding method */
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cghi %r4,64
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jl .Lless_than_64bytes
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.Lfold_64bytes_loop:
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/* Load the next 64-byte data chunk into V5 to V8 */
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VLM %v5,%v8,0,%r3
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/*
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* Perform a GF(2) multiplication of the doublewords in V1 with
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* the reduction constants in V0. The intermediate result is
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* then folded (accumulated) with the next data chunk in V5 and
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* stored in V1. Repeat this step for the register contents
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* in V2, V3, and V4 respectively.
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*/
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VGFMAG %v1,CONST_R1R2,%v1,%v5
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VGFMAG %v2,CONST_R1R2,%v2,%v6
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VGFMAG %v3,CONST_R1R2,%v3,%v7
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VGFMAG %v4,CONST_R1R2,%v4,%v8
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/* Adjust buffer pointer and length for next loop */
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aghi %r3,64 /* BUF = BUF + 64 */
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aghi %r4,-64 /* LEN = LEN - 64 */
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cghi %r4,64
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jnl .Lfold_64bytes_loop
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.Lless_than_64bytes:
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/* Fold V1 to V4 into a single 128-bit value in V1 */
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VGFMAG %v1,CONST_R3R4,%v1,%v2
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VGFMAG %v1,CONST_R3R4,%v1,%v3
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VGFMAG %v1,CONST_R3R4,%v1,%v4
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/* Check whether to continue with 64-bit folding */
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cghi %r4,16
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jl .Lfinal_fold
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.Lfold_16bytes_loop:
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VL %v2,0,,%r3 /* Load next data chunk */
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VGFMAG %v1,CONST_R3R4,%v1,%v2 /* Fold next data chunk */
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/* Adjust buffer pointer and size for folding next data chunk */
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aghi %r3,16
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aghi %r4,-16
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/* Process remaining data chunks */
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cghi %r4,16
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jnl .Lfold_16bytes_loop
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.Lfinal_fold:
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/*
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* The R5 constant is used to fold a 128-bit value into an 96-bit value
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* that is XORed with the next 96-bit input data chunk. To use a single
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* VGFMG instruction, multiply the rightmost 64-bit with x^32 (1<<32) to
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* form an intermediate 96-bit value (with appended zeros) which is then
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* XORed with the intermediate reduction result.
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*/
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VGFMG %v1,CONST_R5,%v1
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/*
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* Further reduce the remaining 96-bit value to a 64-bit value using a
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* single VGFMG, the rightmost doubleword is multiplied with 0x1. The
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* intermediate result is then XORed with the product of the leftmost
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* doubleword with R6. The result is a 64-bit value and is subject to
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* the Barret reduction.
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*/
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VGFMG %v1,CONST_R6,%v1
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/*
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* The input values to the Barret reduction are the degree-63 polynomial
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* in V1 (R(x)), degree-32 generator polynomial, and the reduction
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* constant u. The Barret reduction result is the CRC value of R(x) mod
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* P(x).
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*
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* The Barret reduction algorithm is defined as:
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*
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* 1. T1(x) = floor( R(x) / x^32 ) GF2MUL u
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* 2. T2(x) = floor( T1(x) / x^32 ) GF2MUL P(x)
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* 3. C(x) = R(x) XOR T2(x) mod x^32
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*
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* Note: To compensate the division by x^32, use the vector unpack
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* instruction to move the leftmost word into the leftmost doubleword
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* of the vector register. The rightmost doubleword is multiplied
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* with zero to not contribute to the intermediate results.
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*/
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/* T1(x) = floor( R(x) / x^32 ) GF2MUL u */
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VUPLLF %v2,%v1
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VGFMG %v2,CONST_RU_POLY,%v2
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/*
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* Compute the GF(2) product of the CRC polynomial in VO with T1(x) in
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* V2 and XOR the intermediate result, T2(x), with the value in V1.
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* The final result is in the rightmost word of V2.
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*/
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VUPLLF %v2,%v2
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VGFMAG %v2,CONST_CRC_POLY,%v2,%v1
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.Ldone:
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VLGVF %r2,%v2,3
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BR_EX %r14
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ENDPROC(crc32_be_vgfm_16)
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.previous
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