452 lines
13 KiB
C
452 lines
13 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Adjunct processor (AP) interfaces
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*
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* Copyright IBM Corp. 2017
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*
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* Author(s): Tony Krowiak <akrowia@linux.vnet.ibm.com>
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* Martin Schwidefsky <schwidefsky@de.ibm.com>
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* Harald Freudenberger <freude@de.ibm.com>
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*/
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#ifndef _ASM_S390_AP_H_
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#define _ASM_S390_AP_H_
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#include <linux/io.h>
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#include <asm/asm-extable.h>
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/**
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* The ap_qid_t identifier of an ap queue.
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* If the AP facilities test (APFT) facility is available,
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* card and queue index are 8 bit values, otherwise
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* card index is 6 bit and queue index a 4 bit value.
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*/
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typedef unsigned int ap_qid_t;
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#define AP_MKQID(_card, _queue) (((_card) & 0xff) << 8 | ((_queue) & 0xff))
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#define AP_QID_CARD(_qid) (((_qid) >> 8) & 0xff)
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#define AP_QID_QUEUE(_qid) ((_qid) & 0xff)
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/**
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* struct ap_queue_status - Holds the AP queue status.
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* @queue_empty: Shows if queue is empty
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* @replies_waiting: Waiting replies
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* @queue_full: Is 1 if the queue is full
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* @irq_enabled: Shows if interrupts are enabled for the AP
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* @response_code: Holds the 8 bit response code
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*
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* The ap queue status word is returned by all three AP functions
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* (PQAP, NQAP and DQAP). There's a set of flags in the first
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* byte, followed by a 1 byte response code.
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*/
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struct ap_queue_status {
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unsigned int queue_empty : 1;
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unsigned int replies_waiting : 1;
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unsigned int queue_full : 1;
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unsigned int _pad1 : 4;
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unsigned int irq_enabled : 1;
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unsigned int response_code : 8;
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unsigned int _pad2 : 16;
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};
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/*
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* AP queue status reg union to access the reg1
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* register with the lower 32 bits comprising the
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* ap queue status.
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*/
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union ap_queue_status_reg {
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unsigned long value;
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struct {
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u32 _pad;
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struct ap_queue_status status;
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};
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};
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/**
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* ap_intructions_available() - Test if AP instructions are available.
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*
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* Returns true if the AP instructions are installed, otherwise false.
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*/
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static inline bool ap_instructions_available(void)
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{
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unsigned long reg0 = AP_MKQID(0, 0);
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unsigned long reg1 = 0;
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asm volatile(
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" lgr 0,%[reg0]\n" /* qid into gr0 */
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" lghi 1,0\n" /* 0 into gr1 */
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" lghi 2,0\n" /* 0 into gr2 */
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" .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
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"0: la %[reg1],1\n" /* 1 into reg1 */
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"1:\n"
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EX_TABLE(0b, 1b)
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: [reg1] "+&d" (reg1)
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: [reg0] "d" (reg0)
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: "cc", "0", "1", "2");
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return reg1 != 0;
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}
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/**
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* ap_tapq(): Test adjunct processor queue.
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* @qid: The AP queue number
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* @info: Pointer to queue descriptor
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
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{
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union ap_queue_status_reg reg1;
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unsigned long reg2;
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asm volatile(
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" lgr 0,%[qid]\n" /* qid into gr0 */
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" lghi 2,0\n" /* 0 into gr2 */
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" .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
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" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
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" lgr %[reg2],2\n" /* gr2 into reg2 */
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: [reg1] "=&d" (reg1.value), [reg2] "=&d" (reg2)
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: [qid] "d" (qid)
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: "cc", "0", "1", "2");
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if (info)
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*info = reg2;
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return reg1.status;
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}
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/**
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* ap_test_queue(): Test adjunct processor queue.
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* @qid: The AP queue number
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* @tbit: Test facilities bit
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* @info: Pointer to queue descriptor
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_test_queue(ap_qid_t qid,
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int tbit,
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unsigned long *info)
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{
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if (tbit)
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qid |= 1UL << 23; /* set T bit*/
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return ap_tapq(qid, info);
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}
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/**
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* ap_pqap_rapq(): Reset adjunct processor queue.
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* @qid: The AP queue number
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
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{
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unsigned long reg0 = qid | (1UL << 24); /* fc 1UL is RAPQ */
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union ap_queue_status_reg reg1;
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asm volatile(
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" lgr 0,%[reg0]\n" /* qid arg into gr0 */
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" .insn rre,0xb2af0000,0,0\n" /* PQAP(RAPQ) */
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" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
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: [reg1] "=&d" (reg1.value)
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: [reg0] "d" (reg0)
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: "cc", "0", "1");
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return reg1.status;
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}
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/**
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* ap_pqap_zapq(): Reset and zeroize adjunct processor queue.
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* @qid: The AP queue number
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
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{
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unsigned long reg0 = qid | (2UL << 24); /* fc 2UL is ZAPQ */
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union ap_queue_status_reg reg1;
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asm volatile(
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" lgr 0,%[reg0]\n" /* qid arg into gr0 */
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" .insn rre,0xb2af0000,0,0\n" /* PQAP(ZAPQ) */
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" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
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: [reg1] "=&d" (reg1.value)
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: [reg0] "d" (reg0)
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: "cc", "0", "1");
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return reg1.status;
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}
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/**
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* struct ap_config_info - convenience struct for AP crypto
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* config info as returned by the ap_qci() function.
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*/
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struct ap_config_info {
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unsigned int apsc : 1; /* S bit */
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unsigned int apxa : 1; /* N bit */
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unsigned int qact : 1; /* C bit */
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unsigned int rc8a : 1; /* R bit */
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unsigned char _reserved1 : 4;
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unsigned char _reserved2[3];
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unsigned char Na; /* max # of APs - 1 */
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unsigned char Nd; /* max # of Domains - 1 */
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unsigned char _reserved3[10];
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unsigned int apm[8]; /* AP ID mask */
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unsigned int aqm[8]; /* AP (usage) queue mask */
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unsigned int adm[8]; /* AP (control) domain mask */
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unsigned char _reserved4[16];
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} __aligned(8);
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/**
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* ap_qci(): Get AP configuration data
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*
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* Returns 0 on success, or -EOPNOTSUPP.
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*/
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static inline int ap_qci(struct ap_config_info *config)
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{
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unsigned long reg0 = 4UL << 24; /* fc 4UL is QCI */
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unsigned long reg1 = -EOPNOTSUPP;
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struct ap_config_info *reg2 = config;
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asm volatile(
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" lgr 0,%[reg0]\n" /* QCI fc into gr0 */
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" lgr 2,%[reg2]\n" /* ptr to config into gr2 */
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" .insn rre,0xb2af0000,0,0\n" /* PQAP(QCI) */
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"0: la %[reg1],0\n" /* good case, QCI fc available */
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"1:\n"
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EX_TABLE(0b, 1b)
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: [reg1] "+&d" (reg1)
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: [reg0] "d" (reg0), [reg2] "d" (reg2)
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: "cc", "memory", "0", "2");
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return reg1;
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}
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/*
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* struct ap_qirq_ctrl - convenient struct for easy invocation
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* of the ap_aqic() function. This struct is passed as GR1
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* parameter to the PQAP(AQIC) instruction. For details please
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* see the AR documentation.
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*/
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union ap_qirq_ctrl {
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unsigned long value;
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struct {
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unsigned int : 8;
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unsigned int zone : 8; /* zone info */
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unsigned int ir : 1; /* ir flag: enable (1) or disable (0) irq */
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unsigned int : 4;
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unsigned int gisc : 3; /* guest isc field */
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unsigned int : 6;
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unsigned int gf : 2; /* gisa format */
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unsigned int : 1;
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unsigned int gisa : 27; /* gisa origin */
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unsigned int : 1;
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unsigned int isc : 3; /* irq sub class */
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};
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};
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/**
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* ap_aqic(): Control interruption for a specific AP.
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* @qid: The AP queue number
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* @qirqctrl: struct ap_qirq_ctrl (64 bit value)
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* @pa_ind: Physical address of the notification indicator byte
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*
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* Returns AP queue status.
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*/
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static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
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union ap_qirq_ctrl qirqctrl,
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phys_addr_t pa_ind)
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{
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unsigned long reg0 = qid | (3UL << 24); /* fc 3UL is AQIC */
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union ap_queue_status_reg reg1;
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unsigned long reg2 = pa_ind;
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reg1.value = qirqctrl.value;
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asm volatile(
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" lgr 0,%[reg0]\n" /* qid param into gr0 */
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" lgr 1,%[reg1]\n" /* irq ctrl into gr1 */
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" lgr 2,%[reg2]\n" /* ni addr into gr2 */
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" .insn rre,0xb2af0000,0,0\n" /* PQAP(AQIC) */
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" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
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: [reg1] "+&d" (reg1.value)
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: [reg0] "d" (reg0), [reg2] "d" (reg2)
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: "cc", "memory", "0", "1", "2");
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return reg1.status;
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}
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/*
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* union ap_qact_ap_info - used together with the
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* ap_aqic() function to provide a convenient way
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* to handle the ap info needed by the qact function.
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*/
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union ap_qact_ap_info {
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unsigned long val;
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struct {
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unsigned int : 3;
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unsigned int mode : 3;
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unsigned int : 26;
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unsigned int cat : 8;
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unsigned int : 8;
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unsigned char ver[2];
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};
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};
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/**
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* ap_qact(): Query AP combatibility type.
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* @qid: The AP queue number
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* @apinfo: On input the info about the AP queue. On output the
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* alternate AP queue info provided by the qact function
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* in GR2 is stored in.
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*
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* Returns AP queue status. Check response_code field for failures.
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*/
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static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
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union ap_qact_ap_info *apinfo)
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{
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unsigned long reg0 = qid | (5UL << 24) | ((ifbit & 0x01) << 22);
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union ap_queue_status_reg reg1;
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unsigned long reg2;
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reg1.value = apinfo->val;
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asm volatile(
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" lgr 0,%[reg0]\n" /* qid param into gr0 */
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" lgr 1,%[reg1]\n" /* qact in info into gr1 */
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" .insn rre,0xb2af0000,0,0\n" /* PQAP(QACT) */
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" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
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" lgr %[reg2],2\n" /* qact out info into reg2 */
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: [reg1] "+&d" (reg1.value), [reg2] "=&d" (reg2)
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: [reg0] "d" (reg0)
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: "cc", "0", "1", "2");
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apinfo->val = reg2;
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return reg1.status;
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}
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/**
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* ap_nqap(): Send message to adjunct processor queue.
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* @qid: The AP queue number
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* @psmid: The program supplied message identifier
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* @msg: The message text
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* @length: The message length
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*
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* Returns AP queue status structure.
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* Condition code 1 on NQAP can't happen because the L bit is 1.
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* Condition code 2 on NQAP also means the send is incomplete,
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* because a segment boundary was reached. The NQAP is repeated.
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*/
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static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
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unsigned long long psmid,
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void *msg, size_t length)
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{
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unsigned long reg0 = qid | 0x40000000UL; /* 0x4... is last msg part */
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union register_pair nqap_r1, nqap_r2;
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union ap_queue_status_reg reg1;
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nqap_r1.even = (unsigned int)(psmid >> 32);
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nqap_r1.odd = psmid & 0xffffffff;
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nqap_r2.even = (unsigned long)msg;
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nqap_r2.odd = (unsigned long)length;
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asm volatile (
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" lgr 0,%[reg0]\n" /* qid param in gr0 */
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"0: .insn rre,0xb2ad0000,%[nqap_r1],%[nqap_r2]\n"
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" brc 2,0b\n" /* handle partial completion */
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" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
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: [reg0] "+&d" (reg0), [reg1] "=&d" (reg1.value),
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||
|
|
[nqap_r2] "+&d" (nqap_r2.pair)
|
||
|
|
: [nqap_r1] "d" (nqap_r1.pair)
|
||
|
|
: "cc", "memory", "0", "1");
|
||
|
|
return reg1.status;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* ap_dqap(): Receive message from adjunct processor queue.
|
||
|
|
* @qid: The AP queue number
|
||
|
|
* @psmid: Pointer to program supplied message identifier
|
||
|
|
* @msg: The message text
|
||
|
|
* @length: The message length
|
||
|
|
* @reslength: Resitual length on return
|
||
|
|
* @resgr0: input: gr0 value (only used if != 0), output: resitual gr0 content
|
||
|
|
*
|
||
|
|
* Returns AP queue status structure.
|
||
|
|
* Condition code 1 on DQAP means the receive has taken place
|
||
|
|
* but only partially. The response is incomplete, hence the
|
||
|
|
* DQAP is repeated.
|
||
|
|
* Condition code 2 on DQAP also means the receive is incomplete,
|
||
|
|
* this time because a segment boundary was reached. Again, the
|
||
|
|
* DQAP is repeated.
|
||
|
|
* Note that gpr2 is used by the DQAP instruction to keep track of
|
||
|
|
* any 'residual' length, in case the instruction gets interrupted.
|
||
|
|
* Hence it gets zeroed before the instruction.
|
||
|
|
* If the message does not fit into the buffer, this function will
|
||
|
|
* return with a truncated message and the reply in the firmware queue
|
||
|
|
* is not removed. This is indicated to the caller with an
|
||
|
|
* ap_queue_status response_code value of all bits on (0xFF) and (if
|
||
|
|
* the reslength ptr is given) the remaining length is stored in
|
||
|
|
* *reslength and (if the resgr0 ptr is given) the updated gr0 value
|
||
|
|
* for further processing of this msg entry is stored in *resgr0. The
|
||
|
|
* caller needs to detect this situation and should invoke ap_dqap
|
||
|
|
* with a valid resgr0 ptr and a value in there != 0 to indicate that
|
||
|
|
* *resgr0 is to be used instead of qid to further process this entry.
|
||
|
|
*/
|
||
|
|
static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
|
||
|
|
unsigned long long *psmid,
|
||
|
|
void *msg, size_t length,
|
||
|
|
size_t *reslength,
|
||
|
|
unsigned long *resgr0)
|
||
|
|
{
|
||
|
|
unsigned long reg0 = resgr0 && *resgr0 ? *resgr0 : qid | 0x80000000UL;
|
||
|
|
union ap_queue_status_reg reg1;
|
||
|
|
unsigned long reg2;
|
||
|
|
union register_pair rp1, rp2;
|
||
|
|
|
||
|
|
rp1.even = 0UL;
|
||
|
|
rp1.odd = 0UL;
|
||
|
|
rp2.even = (unsigned long)msg;
|
||
|
|
rp2.odd = (unsigned long)length;
|
||
|
|
|
||
|
|
asm volatile(
|
||
|
|
" lgr 0,%[reg0]\n" /* qid param into gr0 */
|
||
|
|
" lghi 2,0\n" /* 0 into gr2 (res length) */
|
||
|
|
"0: ltgr %N[rp2],%N[rp2]\n" /* check buf len */
|
||
|
|
" jz 2f\n" /* go out if buf len is 0 */
|
||
|
|
"1: .insn rre,0xb2ae0000,%[rp1],%[rp2]\n"
|
||
|
|
" brc 6,0b\n" /* handle partial complete */
|
||
|
|
"2: lgr %[reg0],0\n" /* gr0 (qid + info) into reg0 */
|
||
|
|
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
|
||
|
|
" lgr %[reg2],2\n" /* gr2 (res length) into reg2 */
|
||
|
|
: [reg0] "+&d" (reg0), [reg1] "=&d" (reg1.value),
|
||
|
|
[reg2] "=&d" (reg2), [rp1] "+&d" (rp1.pair),
|
||
|
|
[rp2] "+&d" (rp2.pair)
|
||
|
|
:
|
||
|
|
: "cc", "memory", "0", "1", "2");
|
||
|
|
|
||
|
|
if (reslength)
|
||
|
|
*reslength = reg2;
|
||
|
|
if (reg2 != 0 && rp2.odd == 0) {
|
||
|
|
/*
|
||
|
|
* Partially complete, status in gr1 is not set.
|
||
|
|
* Signal the caller that this dqap is only partially received
|
||
|
|
* with a special status response code 0xFF and *resgr0 updated
|
||
|
|
*/
|
||
|
|
reg1.status.response_code = 0xFF;
|
||
|
|
if (resgr0)
|
||
|
|
*resgr0 = reg0;
|
||
|
|
} else {
|
||
|
|
*psmid = (((unsigned long long)rp1.even) << 32) + rp1.odd;
|
||
|
|
if (resgr0)
|
||
|
|
*resgr0 = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
return reg1.status;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Interface to tell the AP bus code that a configuration
|
||
|
|
* change has happened. The bus code should at least do
|
||
|
|
* an ap bus resource rescan.
|
||
|
|
*/
|
||
|
|
#if IS_ENABLED(CONFIG_ZCRYPT)
|
||
|
|
void ap_bus_cfg_chg(void);
|
||
|
|
#else
|
||
|
|
static inline void ap_bus_cfg_chg(void){}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _ASM_S390_AP_H_ */
|