100 lines
1.7 KiB
Plaintext
100 lines
1.7 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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/ {
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compatible = "jcore,j2-soc";
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model = "J2 FPGA SoC on Mimas v2 board";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&aic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "jcore,j2";
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reg = <0>;
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clock-frequency = <50000000>;
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d-cache-size = <8192>;
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i-cache-size = <8192>;
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d-cache-block-size = <16>;
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i-cache-block-size = <16>;
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};
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};
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memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0x4000000>;
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};
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aliases {
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serial0 = &uart0;
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spi0 = &spi0;
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};
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chosen {
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stdout-path = "serial0";
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};
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soc@abcd0000 {
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compatible = "simple-bus";
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ranges = <0 0xabcd0000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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aic: interrupt-controller@200 {
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compatible = "jcore,aic1";
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reg = <0x200 0x10>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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cache-controller@c0 {
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compatible = "jcore,cache";
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reg = <0xc0 4>;
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};
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timer@200 {
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compatible = "jcore,pit";
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reg = <0x200 0x30>;
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interrupts = <0x48>;
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};
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spi0: spi@40 {
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compatible = "jcore,spi2";
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#address-cells = <1>;
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#size-cells = <0>;
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spi-max-frequency = <25000000>;
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reg = <0x40 0x8>;
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sdcard@0 {
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compatible = "mmc-spi-slot";
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reg = <0>;
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spi-max-frequency = <25000000>;
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voltage-ranges = <3200 3400>;
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mode = <0>;
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};
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};
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uart0: serial@100 {
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clock-frequency = <125000000>;
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compatible = "xlnx,xps-uartlite-1.00.a";
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current-speed = <19200>;
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xlnx,use-parity = <0>;
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xlnx,data-bits = <8>;
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device_type = "serial";
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interrupts = <0x12>;
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port-number = <0>;
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reg = <0x100 0x10>;
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};
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};
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};
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