409 lines
8.2 KiB
C
409 lines
8.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/sh/kernel/hw_breakpoint.c
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*
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* Unified kernel/user-space hardware breakpoint facility for the on-chip UBC.
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*
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* Copyright (C) 2009 - 2010 Paul Mundt
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*/
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#include <linux/init.h>
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#include <linux/perf_event.h>
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#include <linux/sched/signal.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/percpu.h>
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#include <linux/kallsyms.h>
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#include <linux/notifier.h>
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#include <linux/kprobes.h>
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#include <linux/kdebug.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/mmu_context.h>
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#include <asm/ptrace.h>
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#include <asm/traps.h>
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/*
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* Stores the breakpoints currently in use on each breakpoint address
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* register for each cpus
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*/
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static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
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/*
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* A dummy placeholder for early accesses until the CPUs get a chance to
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* register their UBCs later in the boot process.
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*/
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static struct sh_ubc ubc_dummy = { .num_events = 0 };
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static struct sh_ubc *sh_ubc __read_mostly = &ubc_dummy;
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/*
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* Install a perf counter breakpoint.
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*
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* We seek a free UBC channel and use it for this breakpoint.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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int arch_install_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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int i;
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for (i = 0; i < sh_ubc->num_events; i++) {
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struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
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if (!*slot) {
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*slot = bp;
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break;
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}
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}
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if (WARN_ONCE(i == sh_ubc->num_events, "Can't find any breakpoint slot"))
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return -EBUSY;
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clk_enable(sh_ubc->clk);
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sh_ubc->enable(info, i);
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return 0;
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}
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/*
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* Uninstall the breakpoint contained in the given counter.
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*
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* First we search the debug address register it uses and then we disable
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* it.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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void arch_uninstall_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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int i;
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for (i = 0; i < sh_ubc->num_events; i++) {
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struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
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if (*slot == bp) {
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*slot = NULL;
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break;
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}
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}
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if (WARN_ONCE(i == sh_ubc->num_events, "Can't find any breakpoint slot"))
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return;
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sh_ubc->disable(info, i);
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clk_disable(sh_ubc->clk);
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}
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static int get_hbp_len(u16 hbp_len)
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{
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unsigned int len_in_bytes = 0;
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switch (hbp_len) {
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case SH_BREAKPOINT_LEN_1:
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len_in_bytes = 1;
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break;
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case SH_BREAKPOINT_LEN_2:
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len_in_bytes = 2;
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break;
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case SH_BREAKPOINT_LEN_4:
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len_in_bytes = 4;
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break;
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case SH_BREAKPOINT_LEN_8:
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len_in_bytes = 8;
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break;
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}
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return len_in_bytes;
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}
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/*
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* Check for virtual address in kernel space.
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*/
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int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
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{
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unsigned int len;
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unsigned long va;
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va = hw->address;
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len = get_hbp_len(hw->len);
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return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
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}
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int arch_bp_generic_fields(int sh_len, int sh_type,
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int *gen_len, int *gen_type)
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{
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/* Len */
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switch (sh_len) {
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case SH_BREAKPOINT_LEN_1:
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*gen_len = HW_BREAKPOINT_LEN_1;
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break;
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case SH_BREAKPOINT_LEN_2:
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*gen_len = HW_BREAKPOINT_LEN_2;
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break;
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case SH_BREAKPOINT_LEN_4:
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*gen_len = HW_BREAKPOINT_LEN_4;
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break;
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case SH_BREAKPOINT_LEN_8:
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*gen_len = HW_BREAKPOINT_LEN_8;
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break;
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default:
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return -EINVAL;
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}
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/* Type */
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switch (sh_type) {
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case SH_BREAKPOINT_READ:
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*gen_type = HW_BREAKPOINT_R;
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break;
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case SH_BREAKPOINT_WRITE:
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*gen_type = HW_BREAKPOINT_W;
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break;
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case SH_BREAKPOINT_RW:
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*gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int arch_build_bp_info(struct perf_event *bp,
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const struct perf_event_attr *attr,
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struct arch_hw_breakpoint *hw)
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{
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hw->address = attr->bp_addr;
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/* Len */
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switch (attr->bp_len) {
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case HW_BREAKPOINT_LEN_1:
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hw->len = SH_BREAKPOINT_LEN_1;
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break;
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case HW_BREAKPOINT_LEN_2:
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hw->len = SH_BREAKPOINT_LEN_2;
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break;
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case HW_BREAKPOINT_LEN_4:
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hw->len = SH_BREAKPOINT_LEN_4;
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break;
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case HW_BREAKPOINT_LEN_8:
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hw->len = SH_BREAKPOINT_LEN_8;
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break;
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default:
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return -EINVAL;
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}
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/* Type */
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switch (attr->bp_type) {
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case HW_BREAKPOINT_R:
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hw->type = SH_BREAKPOINT_READ;
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break;
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case HW_BREAKPOINT_W:
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hw->type = SH_BREAKPOINT_WRITE;
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break;
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case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
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hw->type = SH_BREAKPOINT_RW;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Validate the arch-specific HW Breakpoint register settings
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*/
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int hw_breakpoint_arch_parse(struct perf_event *bp,
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const struct perf_event_attr *attr,
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struct arch_hw_breakpoint *hw)
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{
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unsigned int align;
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int ret;
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ret = arch_build_bp_info(bp, attr, hw);
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if (ret)
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return ret;
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ret = -EINVAL;
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switch (hw->len) {
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case SH_BREAKPOINT_LEN_1:
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align = 0;
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break;
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case SH_BREAKPOINT_LEN_2:
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align = 1;
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break;
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case SH_BREAKPOINT_LEN_4:
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align = 3;
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break;
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case SH_BREAKPOINT_LEN_8:
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align = 7;
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break;
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default:
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return ret;
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}
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/*
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* Check that the low-order bits of the address are appropriate
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* for the alignment implied by len.
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*/
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if (hw->address & align)
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return -EINVAL;
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return 0;
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}
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/*
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* Release the user breakpoints used by ptrace
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*/
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void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
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{
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int i;
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struct thread_struct *t = &tsk->thread;
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for (i = 0; i < sh_ubc->num_events; i++) {
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unregister_hw_breakpoint(t->ptrace_bps[i]);
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t->ptrace_bps[i] = NULL;
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}
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}
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static int __kprobes hw_breakpoint_handler(struct die_args *args)
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{
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int cpu, i, rc = NOTIFY_STOP;
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struct perf_event *bp;
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unsigned int cmf, resume_mask;
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/*
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* Do an early return if none of the channels triggered.
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*/
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cmf = sh_ubc->triggered_mask();
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if (unlikely(!cmf))
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return NOTIFY_DONE;
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/*
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* By default, resume all of the active channels.
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*/
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resume_mask = sh_ubc->active_mask();
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/*
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* Disable breakpoints during exception handling.
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*/
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sh_ubc->disable_all();
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cpu = get_cpu();
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for (i = 0; i < sh_ubc->num_events; i++) {
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unsigned long event_mask = (1 << i);
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if (likely(!(cmf & event_mask)))
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continue;
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/*
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* The counter may be concurrently released but that can only
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* occur from a call_rcu() path. We can then safely fetch
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* the breakpoint, use its callback, touch its counter
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* while we are in an rcu_read_lock() path.
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*/
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rcu_read_lock();
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bp = per_cpu(bp_per_reg[i], cpu);
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if (bp)
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rc = NOTIFY_DONE;
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/*
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* Reset the condition match flag to denote completion of
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* exception handling.
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*/
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sh_ubc->clear_triggered_mask(event_mask);
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/*
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* bp can be NULL due to concurrent perf counter
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* removing.
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*/
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if (!bp) {
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rcu_read_unlock();
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break;
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}
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/*
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* Don't restore the channel if the breakpoint is from
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* ptrace, as it always operates in one-shot mode.
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*/
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if (bp->overflow_handler == ptrace_triggered)
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resume_mask &= ~(1 << i);
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perf_bp_event(bp, args->regs);
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/* Deliver the signal to userspace */
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if (!arch_check_bp_in_kernelspace(&bp->hw.info)) {
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force_sig_fault(SIGTRAP, TRAP_HWBKPT,
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(void __user *)NULL);
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}
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rcu_read_unlock();
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}
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if (cmf == 0)
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rc = NOTIFY_DONE;
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sh_ubc->enable_all(resume_mask);
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put_cpu();
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return rc;
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}
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BUILD_TRAP_HANDLER(breakpoint)
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{
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unsigned long ex = lookup_exception_vector();
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TRAP_HANDLER_DECL;
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notify_die(DIE_BREAKPOINT, "breakpoint", regs, 0, ex, SIGTRAP);
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}
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/*
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* Handle debug exception notifications.
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*/
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int __kprobes hw_breakpoint_exceptions_notify(struct notifier_block *unused,
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unsigned long val, void *data)
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{
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struct die_args *args = data;
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if (val != DIE_BREAKPOINT)
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return NOTIFY_DONE;
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/*
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* If the breakpoint hasn't been triggered by the UBC, it's
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* probably from a debugger, so don't do anything more here.
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*
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* This also permits the UBC interface clock to remain off for
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* non-UBC breakpoints, as we don't need to check the triggered
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* or active channel masks.
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*/
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if (args->trapnr != sh_ubc->trap_nr)
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return NOTIFY_DONE;
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return hw_breakpoint_handler(data);
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}
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void hw_breakpoint_pmu_read(struct perf_event *bp)
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{
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/* TODO */
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}
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int register_sh_ubc(struct sh_ubc *ubc)
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{
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/* Bail if it's already assigned */
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if (sh_ubc != &ubc_dummy)
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return -EBUSY;
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sh_ubc = ubc;
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pr_info("HW Breakpoints: %s UBC support registered\n", ubc->name);
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|
|
||
|
|
WARN_ON(ubc->num_events > HBP_NUM);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|