423 lines
11 KiB
C
423 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/jump_label.h>
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#include <asm/unwind_hints.h>
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#include <asm/cpufeatures.h>
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#include <asm/page_types.h>
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#include <asm/percpu.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor-flags.h>
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#include <asm/ptrace-abi.h>
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#include <asm/msr.h>
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#include <asm/nospec-branch.h>
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/*
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x86 function call convention, 64-bit:
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-------------------------------------
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arguments | callee-saved | extra caller-saved | return
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[callee-clobbered] | | [callee-clobbered] |
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---------------------------------------------------------------------------
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rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
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( rsp is obviously invariant across normal function calls. (gcc can 'merge'
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functions when it sees tail-call optimization possibilities) rflags is
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clobbered. Leftover arguments are passed over the stack frame.)
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[*] In the frame-pointers case rbp is fixed to the stack frame.
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[**] for struct return values wider than 64 bits the return convention is a
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bit more complex: up to 128 bits width we return small structures
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straight in rax, rdx. For structures larger than that (3 words or
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larger) the caller puts a pointer to an on-stack return struct
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[allocated in the caller's stack frame] into the first argument - i.e.
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into rdi. All other arguments shift up by one in this case.
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Fortunately this case is rare in the kernel.
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For 32-bit we have the following conventions - kernel is built with
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-mregparm=3 and -freg-struct-return:
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x86 function calling convention, 32-bit:
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----------------------------------------
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arguments | callee-saved | extra caller-saved | return
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[callee-clobbered] | | [callee-clobbered] |
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-------------------------------------------------------------------------
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eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
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( here too esp is obviously invariant across normal function calls. eflags
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is clobbered. Leftover arguments are passed over the stack frame. )
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[*] In the frame-pointers case ebp is fixed to the stack frame.
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[**] We build with -freg-struct-return, which on 32-bit means similar
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semantics as on 64-bit: edx can be used for a second return value
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(i.e. covering integer and structure sizes up to 64 bits) - after that
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it gets more complex and more expensive: 3-word or larger struct returns
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get done in the caller's frame and the pointer to the return struct goes
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into regparm0, i.e. eax - the other arguments shift up and the
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function's register parameters degenerate to regparm=2 in essence.
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*/
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#ifdef CONFIG_X86_64
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/*
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* 64-bit system call stack frame layout defines and helpers,
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* for assembly code:
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*/
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.macro PUSH_REGS rdx=%rdx rcx=%rcx rax=%rax save_ret=0
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.if \save_ret
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pushq %rsi /* pt_regs->si */
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movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */
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movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */
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.else
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pushq %rdi /* pt_regs->di */
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pushq %rsi /* pt_regs->si */
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.endif
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pushq \rdx /* pt_regs->dx */
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pushq \rcx /* pt_regs->cx */
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pushq \rax /* pt_regs->ax */
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pushq %r8 /* pt_regs->r8 */
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pushq %r9 /* pt_regs->r9 */
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pushq %r10 /* pt_regs->r10 */
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pushq %r11 /* pt_regs->r11 */
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pushq %rbx /* pt_regs->rbx */
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pushq %rbp /* pt_regs->rbp */
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pushq %r12 /* pt_regs->r12 */
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pushq %r13 /* pt_regs->r13 */
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pushq %r14 /* pt_regs->r14 */
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pushq %r15 /* pt_regs->r15 */
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UNWIND_HINT_REGS
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.if \save_ret
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pushq %rsi /* return address on top of stack */
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.endif
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.endm
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.macro CLEAR_REGS
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/*
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* Sanitize registers of values that a speculation attack might
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* otherwise want to exploit. The lower registers are likely clobbered
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* well before they could be put to use in a speculative execution
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* gadget.
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*/
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xorl %esi, %esi /* nospec si */
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xorl %edx, %edx /* nospec dx */
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xorl %ecx, %ecx /* nospec cx */
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xorl %r8d, %r8d /* nospec r8 */
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xorl %r9d, %r9d /* nospec r9 */
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xorl %r10d, %r10d /* nospec r10 */
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xorl %r11d, %r11d /* nospec r11 */
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xorl %ebx, %ebx /* nospec rbx */
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xorl %ebp, %ebp /* nospec rbp */
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xorl %r12d, %r12d /* nospec r12 */
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xorl %r13d, %r13d /* nospec r13 */
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xorl %r14d, %r14d /* nospec r14 */
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xorl %r15d, %r15d /* nospec r15 */
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.endm
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.macro PUSH_AND_CLEAR_REGS rdx=%rdx rcx=%rcx rax=%rax save_ret=0
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PUSH_REGS rdx=\rdx, rcx=\rcx, rax=\rax, save_ret=\save_ret
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CLEAR_REGS
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.endm
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.macro POP_REGS pop_rdi=1
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popq %r15
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popq %r14
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popq %r13
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popq %r12
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popq %rbp
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popq %rbx
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popq %r11
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popq %r10
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popq %r9
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popq %r8
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popq %rax
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popq %rcx
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popq %rdx
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popq %rsi
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.if \pop_rdi
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popq %rdi
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.endif
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.endm
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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/*
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* PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
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* halves:
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*/
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#define PTI_USER_PGTABLE_BIT PAGE_SHIFT
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#define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
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#define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
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#define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
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#define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
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.macro SET_NOFLUSH_BIT reg:req
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bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
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.endm
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.macro ADJUST_KERNEL_CR3 reg:req
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ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
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/* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
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andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
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.endm
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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mov %cr3, \scratch_reg
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ADJUST_KERNEL_CR3 \scratch_reg
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mov \scratch_reg, %cr3
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.Lend_\@:
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.endm
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#define THIS_CPU_user_pcid_flush_mask \
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PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
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.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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mov %cr3, \scratch_reg
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ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
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/*
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* Test if the ASID needs a flush.
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*/
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movq \scratch_reg, \scratch_reg2
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andq $(0x7FF), \scratch_reg /* mask ASID */
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bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jnc .Lnoflush_\@
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/* Flush needed, clear the bit */
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btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
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movq \scratch_reg2, \scratch_reg
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jmp .Lwrcr3_pcid_\@
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.Lnoflush_\@:
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movq \scratch_reg2, \scratch_reg
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SET_NOFLUSH_BIT \scratch_reg
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.Lwrcr3_pcid_\@:
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/* Flip the ASID to the user version */
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orq $(PTI_USER_PCID_MASK), \scratch_reg
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.Lwrcr3_\@:
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/* Flip the PGD to the user version */
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orq $(PTI_USER_PGTABLE_MASK), \scratch_reg
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mov \scratch_reg, %cr3
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.Lend_\@:
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.endm
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.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
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pushq %rax
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SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
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popq %rax
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.endm
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.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
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ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
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movq %cr3, \scratch_reg
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movq \scratch_reg, \save_reg
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/*
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* Test the user pagetable bit. If set, then the user page tables
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* are active. If clear CR3 already has the kernel page table
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* active.
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*/
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bt $PTI_USER_PGTABLE_BIT, \scratch_reg
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jnc .Ldone_\@
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ADJUST_KERNEL_CR3 \scratch_reg
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movq \scratch_reg, %cr3
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.Ldone_\@:
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.endm
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.macro RESTORE_CR3 scratch_reg:req save_reg:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
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/*
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* KERNEL pages can always resume with NOFLUSH as we do
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* explicit flushes.
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*/
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bt $PTI_USER_PGTABLE_BIT, \save_reg
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jnc .Lnoflush_\@
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/*
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* Check if there's a pending flush for the user ASID we're
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* about to set.
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*/
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movq \save_reg, \scratch_reg
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andq $(0x7FF), \scratch_reg
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bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jnc .Lnoflush_\@
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btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jmp .Lwrcr3_\@
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.Lnoflush_\@:
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SET_NOFLUSH_BIT \save_reg
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.Lwrcr3_\@:
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/*
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* The CR3 write could be avoided when not changing its value,
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* but would require a CR3 read *and* a scratch register.
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*/
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movq \save_reg, %cr3
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.Lend_\@:
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.endm
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#else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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.endm
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.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
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.endm
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.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
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.endm
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.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
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.endm
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.macro RESTORE_CR3 scratch_reg:req save_reg:req
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.endm
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#endif
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/*
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* IBRS kernel mitigation for Spectre_v2.
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*
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* Assumes full context is established (PUSH_REGS, CR3 and GS) and it clobbers
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* the regs it uses (AX, CX, DX). Must be called before the first RET
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* instruction (NOTE! UNTRAIN_RET includes a RET instruction)
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*
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* The optional argument is used to save/restore the current value,
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* which is used on the paranoid paths.
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*
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* Assumes x86_spec_ctrl_{base,current} to have SPEC_CTRL_IBRS set.
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*/
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.macro IBRS_ENTER save_reg
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#ifdef CONFIG_CPU_IBRS_ENTRY
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
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movl $MSR_IA32_SPEC_CTRL, %ecx
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.ifnb \save_reg
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rdmsr
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shl $32, %rdx
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or %rdx, %rax
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mov %rax, \save_reg
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test $SPEC_CTRL_IBRS, %eax
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jz .Ldo_wrmsr_\@
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lfence
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jmp .Lend_\@
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.Ldo_wrmsr_\@:
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.endif
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movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
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movl %edx, %eax
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shr $32, %rdx
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wrmsr
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.Lend_\@:
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#endif
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.endm
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/*
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* Similar to IBRS_ENTER, requires KERNEL GS,CR3 and clobbers (AX, CX, DX)
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* regs. Must be called after the last RET.
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*/
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.macro IBRS_EXIT save_reg
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#ifdef CONFIG_CPU_IBRS_ENTRY
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
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movl $MSR_IA32_SPEC_CTRL, %ecx
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.ifnb \save_reg
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mov \save_reg, %rdx
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.else
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movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
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andl $(~SPEC_CTRL_IBRS), %edx
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.endif
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movl %edx, %eax
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shr $32, %rdx
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wrmsr
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.Lend_\@:
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#endif
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.endm
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/*
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* Mitigate Spectre v1 for conditional swapgs code paths.
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*
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* FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
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* prevent a speculative swapgs when coming from kernel space.
|
||
|
|
*
|
||
|
|
* FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
|
||
|
|
* to prevent the swapgs from getting speculatively skipped when coming from
|
||
|
|
* user space.
|
||
|
|
*/
|
||
|
|
.macro FENCE_SWAPGS_USER_ENTRY
|
||
|
|
ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
|
||
|
|
.endm
|
||
|
|
.macro FENCE_SWAPGS_KERNEL_ENTRY
|
||
|
|
ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
|
||
|
|
.endm
|
||
|
|
|
||
|
|
.macro STACKLEAK_ERASE_NOCLOBBER
|
||
|
|
#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
|
||
|
|
PUSH_AND_CLEAR_REGS
|
||
|
|
call stackleak_erase
|
||
|
|
POP_REGS
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
.macro SAVE_AND_SET_GSBASE scratch_reg:req save_reg:req
|
||
|
|
rdgsbase \save_reg
|
||
|
|
GET_PERCPU_BASE \scratch_reg
|
||
|
|
wrgsbase \scratch_reg
|
||
|
|
.endm
|
||
|
|
|
||
|
|
#else /* CONFIG_X86_64 */
|
||
|
|
# undef UNWIND_HINT_IRET_REGS
|
||
|
|
# define UNWIND_HINT_IRET_REGS
|
||
|
|
#endif /* !CONFIG_X86_64 */
|
||
|
|
|
||
|
|
.macro STACKLEAK_ERASE
|
||
|
|
#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
|
||
|
|
call stackleak_erase
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
#ifdef CONFIG_SMP
|
||
|
|
|
||
|
|
/*
|
||
|
|
* CPU/node NR is loaded from the limit (size) field of a special segment
|
||
|
|
* descriptor entry in GDT.
|
||
|
|
*/
|
||
|
|
.macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req
|
||
|
|
movq $__CPUNODE_SEG, \reg
|
||
|
|
lsl \reg, \reg
|
||
|
|
.endm
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Fetch the per-CPU GSBASE value for this processor and put it in @reg.
|
||
|
|
* We normally use %gs for accessing per-CPU data, but we are setting up
|
||
|
|
* %gs here and obviously can not use %gs itself to access per-CPU data.
|
||
|
|
*
|
||
|
|
* Do not use RDPID, because KVM loads guest's TSC_AUX on vm-entry and
|
||
|
|
* may not restore the host's value until the CPU returns to userspace.
|
||
|
|
* Thus the kernel would consume a guest's TSC_AUX if an NMI arrives
|
||
|
|
* while running KVM's run loop.
|
||
|
|
*/
|
||
|
|
.macro GET_PERCPU_BASE reg:req
|
||
|
|
LOAD_CPU_AND_NODE_SEG_LIMIT \reg
|
||
|
|
andq $VDSO_CPUNODE_MASK, \reg
|
||
|
|
movq __per_cpu_offset(, \reg, 8), \reg
|
||
|
|
.endm
|
||
|
|
|
||
|
|
#else
|
||
|
|
|
||
|
|
.macro GET_PERCPU_BASE reg:req
|
||
|
|
movq pcpu_unit_offsets(%rip), \reg
|
||
|
|
.endm
|
||
|
|
|
||
|
|
#endif /* CONFIG_SMP */
|