640 lines
19 KiB
C
640 lines
19 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <asm/apicdef.h>
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#include <asm/intel-family.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/perf_event.h>
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#include "../perf_event.h"
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#define UNCORE_PMU_NAME_LEN 32
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#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
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#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
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#define UNCORE_FIXED_EVENT 0xff
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#define UNCORE_PMC_IDX_MAX_GENERIC 8
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#define UNCORE_PMC_IDX_MAX_FIXED 1
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#define UNCORE_PMC_IDX_MAX_FREERUNNING 1
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#define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
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#define UNCORE_PMC_IDX_FREERUNNING (UNCORE_PMC_IDX_FIXED + \
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UNCORE_PMC_IDX_MAX_FIXED)
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#define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FREERUNNING + \
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UNCORE_PMC_IDX_MAX_FREERUNNING)
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#define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx) \
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((dev << 24) | (func << 16) | (type << 8) | idx)
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#define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) | idx)
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#define UNCORE_PCI_DEV_DEV(data) ((data >> 24) & 0xff)
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#define UNCORE_PCI_DEV_FUNC(data) ((data >> 16) & 0xff)
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#define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
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#define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
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#define UNCORE_EXTRA_PCI_DEV 0xff
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#define UNCORE_EXTRA_PCI_DEV_MAX 4
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#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
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#define UNCORE_IGNORE_END -1
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struct pci_extra_dev {
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struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
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};
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struct intel_uncore_ops;
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struct intel_uncore_pmu;
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struct intel_uncore_box;
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struct uncore_event_desc;
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struct freerunning_counters;
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struct intel_uncore_topology;
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struct intel_uncore_type {
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const char *name;
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int num_counters;
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int num_boxes;
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int perf_ctr_bits;
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int fixed_ctr_bits;
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int num_freerunning_types;
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int type_id;
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unsigned perf_ctr;
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unsigned event_ctl;
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unsigned event_mask;
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unsigned event_mask_ext;
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unsigned fixed_ctr;
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unsigned fixed_ctl;
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unsigned box_ctl;
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u64 *box_ctls; /* Unit ctrl addr of the first box of each die */
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union {
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unsigned msr_offset;
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unsigned mmio_offset;
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};
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unsigned mmio_map_size;
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unsigned num_shared_regs:8;
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unsigned single_fixed:1;
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unsigned pair_ctr_ctl:1;
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union {
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unsigned *msr_offsets;
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unsigned *pci_offsets;
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unsigned *mmio_offsets;
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};
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unsigned *box_ids;
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struct event_constraint unconstrainted;
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struct event_constraint *constraints;
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struct intel_uncore_pmu *pmus;
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struct intel_uncore_ops *ops;
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struct uncore_event_desc *event_descs;
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struct freerunning_counters *freerunning;
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const struct attribute_group *attr_groups[4];
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const struct attribute_group **attr_update;
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struct pmu *pmu; /* for custom pmu ops */
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/*
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* Uncore PMU would store relevant platform topology configuration here
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* to identify which platform component each PMON block of that type is
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* supposed to monitor.
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*/
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struct intel_uncore_topology **topology;
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/*
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* Optional callbacks for managing mapping of Uncore units to PMONs
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*/
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int (*get_topology)(struct intel_uncore_type *type);
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void (*set_mapping)(struct intel_uncore_type *type);
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void (*cleanup_mapping)(struct intel_uncore_type *type);
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};
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#define pmu_group attr_groups[0]
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#define format_group attr_groups[1]
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#define events_group attr_groups[2]
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struct intel_uncore_ops {
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void (*init_box)(struct intel_uncore_box *);
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void (*exit_box)(struct intel_uncore_box *);
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void (*disable_box)(struct intel_uncore_box *);
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void (*enable_box)(struct intel_uncore_box *);
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void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
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void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
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u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
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int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
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struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
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struct perf_event *);
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void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
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};
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struct intel_uncore_pmu {
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struct pmu pmu;
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char name[UNCORE_PMU_NAME_LEN];
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int pmu_idx;
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int func_id;
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bool registered;
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atomic_t activeboxes;
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struct intel_uncore_type *type;
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struct intel_uncore_box **boxes;
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};
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struct intel_uncore_extra_reg {
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raw_spinlock_t lock;
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u64 config, config1, config2;
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atomic_t ref;
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};
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struct intel_uncore_box {
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int dieid; /* Logical die ID */
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int n_active; /* number of active events */
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int n_events;
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int cpu; /* cpu to collect events */
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unsigned long flags;
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atomic_t refcnt;
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struct perf_event *events[UNCORE_PMC_IDX_MAX];
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struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
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struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
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unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
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u64 tags[UNCORE_PMC_IDX_MAX];
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struct pci_dev *pci_dev;
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struct intel_uncore_pmu *pmu;
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u64 hrtimer_duration; /* hrtimer timeout for this box */
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struct hrtimer hrtimer;
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struct list_head list;
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struct list_head active_list;
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void __iomem *io_addr;
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struct intel_uncore_extra_reg shared_regs[];
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};
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/* CFL uncore 8th cbox MSRs */
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#define CFL_UNC_CBO_7_PERFEVTSEL0 0xf70
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#define CFL_UNC_CBO_7_PER_CTR0 0xf76
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#define UNCORE_BOX_FLAG_INITIATED 0
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/* event config registers are 8-byte apart */
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#define UNCORE_BOX_FLAG_CTL_OFFS8 1
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/* CFL 8th CBOX has different MSR space */
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#define UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS 2
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struct uncore_event_desc {
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struct device_attribute attr;
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const char *config;
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};
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struct freerunning_counters {
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unsigned int counter_base;
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unsigned int counter_offset;
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unsigned int box_offset;
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unsigned int num_counters;
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unsigned int bits;
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unsigned *box_offsets;
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};
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struct uncore_iio_topology {
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int pci_bus_no;
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int segment;
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};
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struct uncore_upi_topology {
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int die_to;
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int pmu_idx_to;
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int enabled;
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};
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struct intel_uncore_topology {
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int pmu_idx;
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union {
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void *untyped;
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struct uncore_iio_topology *iio;
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struct uncore_upi_topology *upi;
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};
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};
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struct pci2phy_map {
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struct list_head list;
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int segment;
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int pbus_to_dieid[256];
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};
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struct pci2phy_map *__find_pci2phy_map(int segment);
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int uncore_pcibus_to_dieid(struct pci_bus *bus);
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int uncore_die_to_segment(int die);
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int uncore_device_to_die(struct pci_dev *dev);
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ssize_t uncore_event_show(struct device *dev,
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struct device_attribute *attr, char *buf);
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static inline struct intel_uncore_pmu *dev_to_uncore_pmu(struct device *dev)
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{
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return container_of(dev_get_drvdata(dev), struct intel_uncore_pmu, pmu);
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}
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#define to_device_attribute(n) container_of(n, struct device_attribute, attr)
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#define to_dev_ext_attribute(n) container_of(n, struct dev_ext_attribute, attr)
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#define attr_to_ext_attr(n) to_dev_ext_attribute(to_device_attribute(n))
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extern int __uncore_max_dies;
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#define uncore_max_dies() (__uncore_max_dies)
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#define INTEL_UNCORE_EVENT_DESC(_name, _config) \
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{ \
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.attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
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.config = _config, \
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}
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#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
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static ssize_t __uncore_##_var##_show(struct device *dev, \
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struct device_attribute *attr, \
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char *page) \
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{ \
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BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
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return sprintf(page, _format "\n"); \
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} \
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static struct device_attribute format_attr_##_var = \
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__ATTR(_name, 0444, __uncore_##_var##_show, NULL)
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static inline bool uncore_pmc_fixed(int idx)
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{
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return idx == UNCORE_PMC_IDX_FIXED;
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}
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static inline bool uncore_pmc_freerunning(int idx)
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{
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return idx == UNCORE_PMC_IDX_FREERUNNING;
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}
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static inline bool uncore_mmio_is_valid_offset(struct intel_uncore_box *box,
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unsigned long offset)
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{
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if (offset < box->pmu->type->mmio_map_size)
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return true;
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pr_warn_once("perf uncore: Invalid offset 0x%lx exceeds mapped area of %s.\n",
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offset, box->pmu->type->name);
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return false;
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}
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static inline
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unsigned int uncore_mmio_box_ctl(struct intel_uncore_box *box)
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{
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return box->pmu->type->box_ctl +
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box->pmu->type->mmio_offset * box->pmu->pmu_idx;
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}
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static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
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{
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return box->pmu->type->box_ctl;
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}
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static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
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{
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return box->pmu->type->fixed_ctl;
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}
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static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
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{
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return box->pmu->type->fixed_ctr;
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}
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static inline
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unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
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{
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if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
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return idx * 8 + box->pmu->type->event_ctl;
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return idx * 4 + box->pmu->type->event_ctl;
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}
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static inline
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unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
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{
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return idx * 8 + box->pmu->type->perf_ctr;
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}
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static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
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{
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struct intel_uncore_pmu *pmu = box->pmu;
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return pmu->type->msr_offsets ?
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pmu->type->msr_offsets[pmu->pmu_idx] :
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pmu->type->msr_offset * pmu->pmu_idx;
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}
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static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
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{
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if (!box->pmu->type->box_ctl)
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return 0;
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return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
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}
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static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
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{
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if (!box->pmu->type->fixed_ctl)
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return 0;
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return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
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}
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static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
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{
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return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
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}
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/*
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* In the uncore document, there is no event-code assigned to free running
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* counters. Some events need to be defined to indicate the free running
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* counters. The events are encoded as event-code + umask-code.
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*
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* The event-code for all free running counters is 0xff, which is the same as
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* the fixed counters.
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*
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* The umask-code is used to distinguish a fixed counter and a free running
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* counter, and different types of free running counters.
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* - For fixed counters, the umask-code is 0x0X.
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* X indicates the index of the fixed counter, which starts from 0.
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* - For free running counters, the umask-code uses the rest of the space.
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* It would bare the format of 0xXY.
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* X stands for the type of free running counters, which starts from 1.
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* Y stands for the index of free running counters of same type, which
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* starts from 0.
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*
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* For example, there are three types of IIO free running counters on Skylake
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* server, IO CLOCKS counters, BANDWIDTH counters and UTILIZATION counters.
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|
|
* The event-code for all the free running counters is 0xff.
|
||
|
|
* 'ioclk' is the first counter of IO CLOCKS. IO CLOCKS is the first type,
|
||
|
|
* which umask-code starts from 0x10.
|
||
|
|
* So 'ioclk' is encoded as event=0xff,umask=0x10
|
||
|
|
* 'bw_in_port2' is the third counter of BANDWIDTH counters. BANDWIDTH is
|
||
|
|
* the second type, which umask-code starts from 0x20.
|
||
|
|
* So 'bw_in_port2' is encoded as event=0xff,umask=0x22
|
||
|
|
*/
|
||
|
|
static inline unsigned int uncore_freerunning_idx(u64 config)
|
||
|
|
{
|
||
|
|
return ((config >> 8) & 0xf);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define UNCORE_FREERUNNING_UMASK_START 0x10
|
||
|
|
|
||
|
|
static inline unsigned int uncore_freerunning_type(u64 config)
|
||
|
|
{
|
||
|
|
return ((((config >> 8) - UNCORE_FREERUNNING_UMASK_START) >> 4) & 0xf);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline
|
||
|
|
unsigned int uncore_freerunning_counter(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event)
|
||
|
|
{
|
||
|
|
unsigned int type = uncore_freerunning_type(event->hw.config);
|
||
|
|
unsigned int idx = uncore_freerunning_idx(event->hw.config);
|
||
|
|
struct intel_uncore_pmu *pmu = box->pmu;
|
||
|
|
|
||
|
|
return pmu->type->freerunning[type].counter_base +
|
||
|
|
pmu->type->freerunning[type].counter_offset * idx +
|
||
|
|
(pmu->type->freerunning[type].box_offsets ?
|
||
|
|
pmu->type->freerunning[type].box_offsets[pmu->pmu_idx] :
|
||
|
|
pmu->type->freerunning[type].box_offset * pmu->pmu_idx);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline
|
||
|
|
unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
|
||
|
|
{
|
||
|
|
if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
|
||
|
|
return CFL_UNC_CBO_7_PERFEVTSEL0 +
|
||
|
|
(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
|
||
|
|
} else {
|
||
|
|
return box->pmu->type->event_ctl +
|
||
|
|
(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
|
||
|
|
uncore_msr_box_offset(box);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline
|
||
|
|
unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
|
||
|
|
{
|
||
|
|
if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
|
||
|
|
return CFL_UNC_CBO_7_PER_CTR0 +
|
||
|
|
(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
|
||
|
|
} else {
|
||
|
|
return box->pmu->type->perf_ctr +
|
||
|
|
(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
|
||
|
|
uncore_msr_box_offset(box);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline
|
||
|
|
unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
|
||
|
|
{
|
||
|
|
if (box->pci_dev || box->io_addr)
|
||
|
|
return uncore_pci_fixed_ctl(box);
|
||
|
|
else
|
||
|
|
return uncore_msr_fixed_ctl(box);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline
|
||
|
|
unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
|
||
|
|
{
|
||
|
|
if (box->pci_dev || box->io_addr)
|
||
|
|
return uncore_pci_fixed_ctr(box);
|
||
|
|
else
|
||
|
|
return uncore_msr_fixed_ctr(box);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline
|
||
|
|
unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
|
||
|
|
{
|
||
|
|
if (box->pci_dev || box->io_addr)
|
||
|
|
return uncore_pci_event_ctl(box, idx);
|
||
|
|
else
|
||
|
|
return uncore_msr_event_ctl(box, idx);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline
|
||
|
|
unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
|
||
|
|
{
|
||
|
|
if (box->pci_dev || box->io_addr)
|
||
|
|
return uncore_pci_perf_ctr(box, idx);
|
||
|
|
else
|
||
|
|
return uncore_msr_perf_ctr(box, idx);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
|
||
|
|
{
|
||
|
|
return box->pmu->type->perf_ctr_bits;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
|
||
|
|
{
|
||
|
|
return box->pmu->type->fixed_ctr_bits;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline
|
||
|
|
unsigned int uncore_freerunning_bits(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event)
|
||
|
|
{
|
||
|
|
unsigned int type = uncore_freerunning_type(event->hw.config);
|
||
|
|
|
||
|
|
return box->pmu->type->freerunning[type].bits;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int uncore_num_freerunning(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event)
|
||
|
|
{
|
||
|
|
unsigned int type = uncore_freerunning_type(event->hw.config);
|
||
|
|
|
||
|
|
return box->pmu->type->freerunning[type].num_counters;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int uncore_num_freerunning_types(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event)
|
||
|
|
{
|
||
|
|
return box->pmu->type->num_freerunning_types;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool check_valid_freerunning_event(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event)
|
||
|
|
{
|
||
|
|
unsigned int type = uncore_freerunning_type(event->hw.config);
|
||
|
|
unsigned int idx = uncore_freerunning_idx(event->hw.config);
|
||
|
|
|
||
|
|
return (type < uncore_num_freerunning_types(box, event)) &&
|
||
|
|
(idx < uncore_num_freerunning(box, event));
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int uncore_num_counters(struct intel_uncore_box *box)
|
||
|
|
{
|
||
|
|
return box->pmu->type->num_counters;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool is_freerunning_event(struct perf_event *event)
|
||
|
|
{
|
||
|
|
u64 cfg = event->attr.config;
|
||
|
|
|
||
|
|
return ((cfg & UNCORE_FIXED_EVENT) == UNCORE_FIXED_EVENT) &&
|
||
|
|
(((cfg >> 8) & 0xff) >= UNCORE_FREERUNNING_UMASK_START);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check and reject invalid config */
|
||
|
|
static inline int uncore_freerunning_hw_config(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event)
|
||
|
|
{
|
||
|
|
if (is_freerunning_event(event))
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void uncore_disable_event(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event)
|
||
|
|
{
|
||
|
|
box->pmu->type->ops->disable_event(box, event);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void uncore_enable_event(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event)
|
||
|
|
{
|
||
|
|
box->pmu->type->ops->enable_event(box, event);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u64 uncore_read_counter(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event)
|
||
|
|
{
|
||
|
|
return box->pmu->type->ops->read_counter(box, event);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void uncore_box_init(struct intel_uncore_box *box)
|
||
|
|
{
|
||
|
|
if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
|
||
|
|
if (box->pmu->type->ops->init_box)
|
||
|
|
box->pmu->type->ops->init_box(box);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void uncore_box_exit(struct intel_uncore_box *box)
|
||
|
|
{
|
||
|
|
if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
|
||
|
|
if (box->pmu->type->ops->exit_box)
|
||
|
|
box->pmu->type->ops->exit_box(box);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
|
||
|
|
{
|
||
|
|
return (box->dieid < 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
|
||
|
|
{
|
||
|
|
return container_of(event->pmu, struct intel_uncore_pmu, pmu);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
|
||
|
|
{
|
||
|
|
return event->pmu_private;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
|
||
|
|
u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
|
||
|
|
void uncore_mmio_exit_box(struct intel_uncore_box *box);
|
||
|
|
u64 uncore_mmio_read_counter(struct intel_uncore_box *box,
|
||
|
|
struct perf_event *event);
|
||
|
|
void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
|
||
|
|
void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
|
||
|
|
void uncore_pmu_event_start(struct perf_event *event, int flags);
|
||
|
|
void uncore_pmu_event_stop(struct perf_event *event, int flags);
|
||
|
|
int uncore_pmu_event_add(struct perf_event *event, int flags);
|
||
|
|
void uncore_pmu_event_del(struct perf_event *event, int flags);
|
||
|
|
void uncore_pmu_event_read(struct perf_event *event);
|
||
|
|
void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
|
||
|
|
struct event_constraint *
|
||
|
|
uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
|
||
|
|
void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
|
||
|
|
u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
|
||
|
|
void uncore_get_alias_name(char *pmu_name, struct intel_uncore_pmu *pmu);
|
||
|
|
|
||
|
|
extern struct intel_uncore_type *empty_uncore[];
|
||
|
|
extern struct intel_uncore_type **uncore_msr_uncores;
|
||
|
|
extern struct intel_uncore_type **uncore_pci_uncores;
|
||
|
|
extern struct intel_uncore_type **uncore_mmio_uncores;
|
||
|
|
extern struct pci_driver *uncore_pci_driver;
|
||
|
|
extern struct pci_driver *uncore_pci_sub_driver;
|
||
|
|
extern raw_spinlock_t pci2phy_map_lock;
|
||
|
|
extern struct list_head pci2phy_map_head;
|
||
|
|
extern struct pci_extra_dev *uncore_extra_pci_dev;
|
||
|
|
extern struct event_constraint uncore_constraint_empty;
|
||
|
|
extern int spr_uncore_units_ignore[];
|
||
|
|
|
||
|
|
/* uncore_snb.c */
|
||
|
|
int snb_uncore_pci_init(void);
|
||
|
|
int ivb_uncore_pci_init(void);
|
||
|
|
int hsw_uncore_pci_init(void);
|
||
|
|
int bdw_uncore_pci_init(void);
|
||
|
|
int skl_uncore_pci_init(void);
|
||
|
|
void snb_uncore_cpu_init(void);
|
||
|
|
void nhm_uncore_cpu_init(void);
|
||
|
|
void skl_uncore_cpu_init(void);
|
||
|
|
void icl_uncore_cpu_init(void);
|
||
|
|
void tgl_uncore_cpu_init(void);
|
||
|
|
void adl_uncore_cpu_init(void);
|
||
|
|
void mtl_uncore_cpu_init(void);
|
||
|
|
void tgl_uncore_mmio_init(void);
|
||
|
|
void tgl_l_uncore_mmio_init(void);
|
||
|
|
void adl_uncore_mmio_init(void);
|
||
|
|
int snb_pci2phy_map_init(int devid);
|
||
|
|
|
||
|
|
/* uncore_snbep.c */
|
||
|
|
int snbep_uncore_pci_init(void);
|
||
|
|
void snbep_uncore_cpu_init(void);
|
||
|
|
int ivbep_uncore_pci_init(void);
|
||
|
|
void ivbep_uncore_cpu_init(void);
|
||
|
|
int hswep_uncore_pci_init(void);
|
||
|
|
void hswep_uncore_cpu_init(void);
|
||
|
|
int bdx_uncore_pci_init(void);
|
||
|
|
void bdx_uncore_cpu_init(void);
|
||
|
|
int knl_uncore_pci_init(void);
|
||
|
|
void knl_uncore_cpu_init(void);
|
||
|
|
int skx_uncore_pci_init(void);
|
||
|
|
void skx_uncore_cpu_init(void);
|
||
|
|
int snr_uncore_pci_init(void);
|
||
|
|
void snr_uncore_cpu_init(void);
|
||
|
|
void snr_uncore_mmio_init(void);
|
||
|
|
int icx_uncore_pci_init(void);
|
||
|
|
void icx_uncore_cpu_init(void);
|
||
|
|
void icx_uncore_mmio_init(void);
|
||
|
|
int spr_uncore_pci_init(void);
|
||
|
|
void spr_uncore_cpu_init(void);
|
||
|
|
void spr_uncore_mmio_init(void);
|
||
|
|
|
||
|
|
/* uncore_nhmex.c */
|
||
|
|
void nhmex_uncore_cpu_init(void);
|