183 lines
6.8 KiB
C
183 lines
6.8 KiB
C
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/*
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* This header file contains assembly-language definitions (assembly
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* macros, etc.) for this specific Xtensa processor's TIE extensions
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* and options. It is customized to this Xtensa processor configuration.
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*
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* This file is subject to the terms and conditions of version 2.1 of the GNU
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* Lesser General Public License as published by the Free Software Foundation.
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*
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* Copyright (C) 1999-2009 Tensilica Inc.
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*/
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#ifndef _XTENSA_CORE_TIE_ASM_H
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#define _XTENSA_CORE_TIE_ASM_H
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/* Selection parameter values for save-area save/restore macros: */
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/* Option vs. TIE: */
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#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
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#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
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/* Whether used automatically by compiler: */
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#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
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#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
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/* ABI handling across function calls: */
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#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
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#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
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#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
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/* Misc */
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Save area ptr (clobbered): ptr (8 byte aligned)
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
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*/
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.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
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xchal_sa_start \continue, \ofs
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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rsr \at1, BR // boolean option
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s32i \at1, \ptr, .Lxchal_ofs_ + 0
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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rsr \at1, SCOMPARE1 // conditional store option
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s32i \at1, \ptr, .Lxchal_ofs_ + 0
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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rur \at1, THREADPTR // threadptr option
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s32i \at1, \ptr, .Lxchal_ofs_ + 0
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.endm // xchal_ncp_store
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Save area ptr (clobbered): ptr (8 byte aligned)
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
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*/
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.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
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xchal_sa_start \continue, \ofs
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_ + 0
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wsr \at1, BR // boolean option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_ + 0
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wsr \at1, SCOMPARE1 // conditional store option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_ + 0
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wur \at1, THREADPTR // threadptr option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.endm // xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS 1
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/* Macro to save the state of TIE coprocessor AudioEngineLX.
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* Save area ptr (clobbered): ptr (8 byte aligned)
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_CP1_NUM_ATMPS needed)
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*/
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#define xchal_cp_AudioEngineLX_store xchal_cp1_store
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/* #define xchal_cp_AudioEngineLX_store_a2 xchal_cp1_store a2 a3 a4 a5 a6 */
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.macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
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xchal_sa_start \continue, \ofs
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.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 0, 1, 8
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rur240 \at1 // AE_OVF_SAR
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s32i \at1, \ptr, 0
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rur241 \at1 // AE_BITHEAD
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s32i \at1, \ptr, 4
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rur242 \at1 // AE_TS_FTS_BU_BP
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s32i \at1, \ptr, 8
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rur243 \at1 // AE_SD_NO
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s32i \at1, \ptr, 12
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AE_SP24X2S.I aep0, \ptr, 16
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AE_SP24X2S.I aep1, \ptr, 24
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AE_SP24X2S.I aep2, \ptr, 32
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AE_SP24X2S.I aep3, \ptr, 40
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AE_SP24X2S.I aep4, \ptr, 48
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AE_SP24X2S.I aep5, \ptr, 56
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addi \ptr, \ptr, 64
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AE_SP24X2S.I aep6, \ptr, 0
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AE_SP24X2S.I aep7, \ptr, 8
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AE_SQ56S.I aeq0, \ptr, 16
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AE_SQ56S.I aeq1, \ptr, 24
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AE_SQ56S.I aeq2, \ptr, 32
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AE_SQ56S.I aeq3, \ptr, 40
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.set .Lxchal_pofs_, .Lxchal_pofs_ + 64
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 112
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.endif
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.endm // xchal_cp1_store
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/* Macro to restore the state of TIE coprocessor AudioEngineLX.
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* Save area ptr (clobbered): ptr (8 byte aligned)
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_CP1_NUM_ATMPS needed)
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*/
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#define xchal_cp_AudioEngineLX_load xchal_cp1_load
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/* #define xchal_cp_AudioEngineLX_load_a2 xchal_cp1_load a2 a3 a4 a5 a6 */
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.macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
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xchal_sa_start \continue, \ofs
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.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 0, 1, 8
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l32i \at1, \ptr, 0
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wur240 \at1 // AE_OVF_SAR
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l32i \at1, \ptr, 4
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wur241 \at1 // AE_BITHEAD
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l32i \at1, \ptr, 8
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wur242 \at1 // AE_TS_FTS_BU_BP
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l32i \at1, \ptr, 12
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wur243 \at1 // AE_SD_NO
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addi \ptr, \ptr, 80
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AE_LQ56.I aeq0, \ptr, 0
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AE_LQ56.I aeq1, \ptr, 8
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AE_LQ56.I aeq2, \ptr, 16
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AE_LQ56.I aeq3, \ptr, 24
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AE_LP24X2.I aep0, \ptr, -64
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AE_LP24X2.I aep1, \ptr, -56
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AE_LP24X2.I aep2, \ptr, -48
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AE_LP24X2.I aep3, \ptr, -40
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AE_LP24X2.I aep4, \ptr, -32
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AE_LP24X2.I aep5, \ptr, -24
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AE_LP24X2.I aep6, \ptr, -16
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AE_LP24X2.I aep7, \ptr, -8
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.set .Lxchal_pofs_, .Lxchal_pofs_ + 80
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 112
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.endif
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.endm // xchal_cp1_load
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#define XCHAL_CP1_NUM_ATMPS 1
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#define XCHAL_SA_NUM_ATMPS 1
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/* Empty macros for unconfigured coprocessors: */
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.macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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#endif /*_XTENSA_CORE_TIE_ASM_H*/
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