53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Copyright (c) 2020 BayLibre, SAS
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* Author: James Liao <jamesjj.liao@mediatek.com>
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* Fabien Parent <fparent@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8167-clk.h>
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static const struct mtk_gate_regs mfg_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_MFG(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate mfg_clks[] __initconst = {
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GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0),
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GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "gfmux_emi1x_sel", 1),
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GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_mm", 2),
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GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3),
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};
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static void __init mtk_mfgcfg_init(struct device_node *node)
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{
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struct clk_hw_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
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mtk_clk_register_gates(NULL, node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data);
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_mfgcfg, "mediatek,mt8167-mfgcfg", mtk_mfgcfg_init);
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