624 lines
16 KiB
C
624 lines
16 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016, Linaro Limited
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/mfd/qcom_rpm.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/mfd/qcom-rpm.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
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#define QCOM_RPM_SCALING_ENABLE_ID 0x2
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#define QCOM_RPM_XO_MODE_ON 0x2
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static const struct clk_parent_data gcc_pxo[] = {
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{ .fw_name = "pxo", .name = "pxo_board" },
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};
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static const struct clk_parent_data gcc_cxo[] = {
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{ .fw_name = "cxo", .name = "cxo_board" },
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};
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#define DEFINE_CLK_RPM(_name, r_id) \
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static struct clk_rpm clk_rpm_##_name##_a_clk; \
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static struct clk_rpm clk_rpm_##_name##_clk = { \
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.rpm_clk_id = (r_id), \
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.peer = &clk_rpm_##_name##_a_clk, \
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.rate = INT_MAX, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_ops, \
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.name = #_name "_clk", \
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.parent_data = gcc_pxo, \
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.num_parents = ARRAY_SIZE(gcc_pxo), \
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}, \
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}; \
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static struct clk_rpm clk_rpm_##_name##_a_clk = { \
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.rpm_clk_id = (r_id), \
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.peer = &clk_rpm_##_name##_clk, \
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.active_only = true, \
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.rate = INT_MAX, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_ops, \
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.name = #_name "_a_clk", \
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.parent_data = gcc_pxo, \
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.num_parents = ARRAY_SIZE(gcc_pxo), \
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}, \
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}
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#define DEFINE_CLK_RPM_XO_BUFFER(_name, offset) \
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static struct clk_rpm clk_rpm_##_name##_clk = { \
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.rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \
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.xo_offset = (offset), \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_xo_ops, \
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.name = #_name "_clk", \
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.parent_data = gcc_cxo, \
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.num_parents = ARRAY_SIZE(gcc_cxo), \
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}, \
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}
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#define DEFINE_CLK_RPM_FIXED(_name, r_id, r) \
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static struct clk_rpm clk_rpm_##_name##_clk = { \
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.rpm_clk_id = (r_id), \
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.rate = (r), \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_fixed_ops, \
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.name = #_name "_clk", \
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.parent_data = gcc_pxo, \
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.num_parents = ARRAY_SIZE(gcc_pxo), \
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}, \
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}
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#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
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struct rpm_cc;
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struct clk_rpm {
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const int rpm_clk_id;
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const int xo_offset;
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const bool active_only;
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unsigned long rate;
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bool enabled;
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bool branch;
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struct clk_rpm *peer;
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struct clk_hw hw;
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struct qcom_rpm *rpm;
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struct rpm_cc *rpm_cc;
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};
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struct rpm_cc {
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struct qcom_rpm *rpm;
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struct clk_rpm **clks;
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size_t num_clks;
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u32 xo_buffer_value;
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struct mutex xo_lock;
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};
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struct rpm_clk_desc {
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struct clk_rpm **clks;
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size_t num_clks;
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};
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static DEFINE_MUTEX(rpm_clk_lock);
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static int clk_rpm_handoff(struct clk_rpm *r)
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{
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int ret;
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u32 value = INT_MAX;
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/*
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* The vendor tree simply reads the status for this
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* RPM clock.
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*/
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if (r->rpm_clk_id == QCOM_RPM_PLL_4 ||
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r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)
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return 0;
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ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
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r->rpm_clk_id, &value, 1);
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if (ret)
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return ret;
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ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
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r->rpm_clk_id, &value, 1);
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if (ret)
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return ret;
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return 0;
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}
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static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
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{
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u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
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return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
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r->rpm_clk_id, &value, 1);
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}
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static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
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{
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u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
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return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
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r->rpm_clk_id, &value, 1);
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}
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static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
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unsigned long *active, unsigned long *sleep)
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{
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*active = rate;
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/*
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* Active-only clocks don't care what the rate is during sleep. So,
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* they vote for zero.
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*/
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if (r->active_only)
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*sleep = 0;
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else
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*sleep = *active;
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}
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static int clk_rpm_prepare(struct clk_hw *hw)
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{
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struct clk_rpm *r = to_clk_rpm(hw);
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struct clk_rpm *peer = r->peer;
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unsigned long this_rate = 0, this_sleep_rate = 0;
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unsigned long peer_rate = 0, peer_sleep_rate = 0;
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unsigned long active_rate, sleep_rate;
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int ret = 0;
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mutex_lock(&rpm_clk_lock);
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/* Don't send requests to the RPM if the rate has not been set. */
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if (!r->rate)
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goto out;
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to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
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/* Take peer clock's rate into account only if it's enabled. */
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if (peer->enabled)
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to_active_sleep(peer, peer->rate,
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&peer_rate, &peer_sleep_rate);
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active_rate = max(this_rate, peer_rate);
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if (r->branch)
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active_rate = !!active_rate;
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ret = clk_rpm_set_rate_active(r, active_rate);
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if (ret)
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goto out;
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sleep_rate = max(this_sleep_rate, peer_sleep_rate);
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if (r->branch)
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sleep_rate = !!sleep_rate;
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ret = clk_rpm_set_rate_sleep(r, sleep_rate);
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if (ret)
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/* Undo the active set vote and restore it */
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ret = clk_rpm_set_rate_active(r, peer_rate);
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out:
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if (!ret)
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r->enabled = true;
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mutex_unlock(&rpm_clk_lock);
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return ret;
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}
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static void clk_rpm_unprepare(struct clk_hw *hw)
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{
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struct clk_rpm *r = to_clk_rpm(hw);
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struct clk_rpm *peer = r->peer;
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unsigned long peer_rate = 0, peer_sleep_rate = 0;
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unsigned long active_rate, sleep_rate;
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int ret;
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mutex_lock(&rpm_clk_lock);
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if (!r->rate)
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goto out;
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/* Take peer clock's rate into account only if it's enabled. */
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if (peer->enabled)
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to_active_sleep(peer, peer->rate, &peer_rate,
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&peer_sleep_rate);
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active_rate = r->branch ? !!peer_rate : peer_rate;
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ret = clk_rpm_set_rate_active(r, active_rate);
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if (ret)
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goto out;
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sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
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ret = clk_rpm_set_rate_sleep(r, sleep_rate);
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if (ret)
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goto out;
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r->enabled = false;
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out:
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mutex_unlock(&rpm_clk_lock);
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}
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static int clk_rpm_xo_prepare(struct clk_hw *hw)
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{
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struct clk_rpm *r = to_clk_rpm(hw);
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struct rpm_cc *rcc = r->rpm_cc;
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int ret, clk_id = r->rpm_clk_id;
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u32 value;
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mutex_lock(&rcc->xo_lock);
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value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset);
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ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
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if (!ret) {
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r->enabled = true;
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rcc->xo_buffer_value = value;
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}
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mutex_unlock(&rcc->xo_lock);
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return ret;
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}
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static void clk_rpm_xo_unprepare(struct clk_hw *hw)
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{
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struct clk_rpm *r = to_clk_rpm(hw);
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struct rpm_cc *rcc = r->rpm_cc;
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int ret, clk_id = r->rpm_clk_id;
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u32 value;
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mutex_lock(&rcc->xo_lock);
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value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);
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ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
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if (!ret) {
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r->enabled = false;
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rcc->xo_buffer_value = value;
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}
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mutex_unlock(&rcc->xo_lock);
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}
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static int clk_rpm_fixed_prepare(struct clk_hw *hw)
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{
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struct clk_rpm *r = to_clk_rpm(hw);
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u32 value = 1;
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int ret;
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ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
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r->rpm_clk_id, &value, 1);
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if (!ret)
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r->enabled = true;
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return ret;
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}
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static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
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{
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struct clk_rpm *r = to_clk_rpm(hw);
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u32 value = 0;
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int ret;
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ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
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r->rpm_clk_id, &value, 1);
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if (!ret)
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r->enabled = false;
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}
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static int clk_rpm_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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struct clk_rpm *r = to_clk_rpm(hw);
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struct clk_rpm *peer = r->peer;
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unsigned long active_rate, sleep_rate;
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unsigned long this_rate = 0, this_sleep_rate = 0;
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unsigned long peer_rate = 0, peer_sleep_rate = 0;
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int ret = 0;
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mutex_lock(&rpm_clk_lock);
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if (!r->enabled)
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goto out;
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to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
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/* Take peer clock's rate into account only if it's enabled. */
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if (peer->enabled)
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to_active_sleep(peer, peer->rate,
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&peer_rate, &peer_sleep_rate);
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active_rate = max(this_rate, peer_rate);
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ret = clk_rpm_set_rate_active(r, active_rate);
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if (ret)
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goto out;
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sleep_rate = max(this_sleep_rate, peer_sleep_rate);
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ret = clk_rpm_set_rate_sleep(r, sleep_rate);
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if (ret)
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goto out;
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r->rate = rate;
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out:
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mutex_unlock(&rpm_clk_lock);
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return ret;
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}
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static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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/*
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* RPM handles rate rounding and we don't have a way to
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* know what the rate will be, so just return whatever
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* rate is requested.
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*/
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return rate;
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}
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static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_rpm *r = to_clk_rpm(hw);
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/*
|
||
|
|
* RPM handles rate rounding and we don't have a way to
|
||
|
|
* know what the rate will be, so just return whatever
|
||
|
|
* rate was set.
|
||
|
|
*/
|
||
|
|
return r->rate;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct clk_ops clk_rpm_xo_ops = {
|
||
|
|
.prepare = clk_rpm_xo_prepare,
|
||
|
|
.unprepare = clk_rpm_xo_unprepare,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct clk_ops clk_rpm_fixed_ops = {
|
||
|
|
.prepare = clk_rpm_fixed_prepare,
|
||
|
|
.unprepare = clk_rpm_fixed_unprepare,
|
||
|
|
.round_rate = clk_rpm_round_rate,
|
||
|
|
.recalc_rate = clk_rpm_recalc_rate,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct clk_ops clk_rpm_ops = {
|
||
|
|
.prepare = clk_rpm_prepare,
|
||
|
|
.unprepare = clk_rpm_unprepare,
|
||
|
|
.set_rate = clk_rpm_set_rate,
|
||
|
|
.round_rate = clk_rpm_round_rate,
|
||
|
|
.recalc_rate = clk_rpm_recalc_rate,
|
||
|
|
};
|
||
|
|
|
||
|
|
DEFINE_CLK_RPM(afab, QCOM_RPM_APPS_FABRIC_CLK);
|
||
|
|
DEFINE_CLK_RPM(sfab, QCOM_RPM_SYS_FABRIC_CLK);
|
||
|
|
DEFINE_CLK_RPM(mmfab, QCOM_RPM_MM_FABRIC_CLK);
|
||
|
|
DEFINE_CLK_RPM(daytona, QCOM_RPM_DAYTONA_FABRIC_CLK);
|
||
|
|
DEFINE_CLK_RPM(sfpb, QCOM_RPM_SFPB_CLK);
|
||
|
|
DEFINE_CLK_RPM(cfpb, QCOM_RPM_CFPB_CLK);
|
||
|
|
DEFINE_CLK_RPM(mmfpb, QCOM_RPM_MMFPB_CLK);
|
||
|
|
DEFINE_CLK_RPM(smi, QCOM_RPM_SMI_CLK);
|
||
|
|
DEFINE_CLK_RPM(ebi1, QCOM_RPM_EBI1_CLK);
|
||
|
|
|
||
|
|
DEFINE_CLK_RPM(qdss, QCOM_RPM_QDSS_CLK);
|
||
|
|
DEFINE_CLK_RPM(nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK);
|
||
|
|
DEFINE_CLK_RPM(nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK);
|
||
|
|
|
||
|
|
DEFINE_CLK_RPM_FIXED(pll4, QCOM_RPM_PLL_4, 540672000);
|
||
|
|
|
||
|
|
DEFINE_CLK_RPM_XO_BUFFER(xo_d0, 0);
|
||
|
|
DEFINE_CLK_RPM_XO_BUFFER(xo_d1, 8);
|
||
|
|
DEFINE_CLK_RPM_XO_BUFFER(xo_a0, 16);
|
||
|
|
DEFINE_CLK_RPM_XO_BUFFER(xo_a1, 24);
|
||
|
|
DEFINE_CLK_RPM_XO_BUFFER(xo_a2, 28);
|
||
|
|
|
||
|
|
static struct clk_rpm *msm8660_clks[] = {
|
||
|
|
[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
|
||
|
|
[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
|
||
|
|
[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
|
||
|
|
[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
|
||
|
|
[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
|
||
|
|
[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
|
||
|
|
[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
|
||
|
|
[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
|
||
|
|
[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
|
||
|
|
[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
|
||
|
|
[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
|
||
|
|
[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
|
||
|
|
[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
|
||
|
|
[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
|
||
|
|
[RPM_SMI_CLK] = &clk_rpm_smi_clk,
|
||
|
|
[RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk,
|
||
|
|
[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
|
||
|
|
[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
|
||
|
|
[RPM_PLL4_CLK] = &clk_rpm_pll4_clk,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct rpm_clk_desc rpm_clk_msm8660 = {
|
||
|
|
.clks = msm8660_clks,
|
||
|
|
.num_clks = ARRAY_SIZE(msm8660_clks),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_rpm *apq8064_clks[] = {
|
||
|
|
[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
|
||
|
|
[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
|
||
|
|
[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
|
||
|
|
[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
|
||
|
|
[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
|
||
|
|
[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
|
||
|
|
[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
|
||
|
|
[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
|
||
|
|
[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
|
||
|
|
[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
|
||
|
|
[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
|
||
|
|
[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
|
||
|
|
[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
|
||
|
|
[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
|
||
|
|
[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
|
||
|
|
[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
|
||
|
|
[RPM_QDSS_CLK] = &clk_rpm_qdss_clk,
|
||
|
|
[RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk,
|
||
|
|
[RPM_XO_D0] = &clk_rpm_xo_d0_clk,
|
||
|
|
[RPM_XO_D1] = &clk_rpm_xo_d1_clk,
|
||
|
|
[RPM_XO_A0] = &clk_rpm_xo_a0_clk,
|
||
|
|
[RPM_XO_A1] = &clk_rpm_xo_a1_clk,
|
||
|
|
[RPM_XO_A2] = &clk_rpm_xo_a2_clk,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct rpm_clk_desc rpm_clk_apq8064 = {
|
||
|
|
.clks = apq8064_clks,
|
||
|
|
.num_clks = ARRAY_SIZE(apq8064_clks),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_rpm *ipq806x_clks[] = {
|
||
|
|
[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
|
||
|
|
[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
|
||
|
|
[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
|
||
|
|
[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
|
||
|
|
[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
|
||
|
|
[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
|
||
|
|
[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
|
||
|
|
[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
|
||
|
|
[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
|
||
|
|
[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
|
||
|
|
[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
|
||
|
|
[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
|
||
|
|
[RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk,
|
||
|
|
[RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk,
|
||
|
|
[RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk,
|
||
|
|
[RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct rpm_clk_desc rpm_clk_ipq806x = {
|
||
|
|
.clks = ipq806x_clks,
|
||
|
|
.num_clks = ARRAY_SIZE(ipq806x_clks),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id rpm_clk_match_table[] = {
|
||
|
|
{ .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
|
||
|
|
{ .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
|
||
|
|
{ .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
|
||
|
|
{ .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
|
||
|
|
|
||
|
|
static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,
|
||
|
|
void *data)
|
||
|
|
{
|
||
|
|
struct rpm_cc *rcc = data;
|
||
|
|
unsigned int idx = clkspec->args[0];
|
||
|
|
|
||
|
|
if (idx >= rcc->num_clks) {
|
||
|
|
pr_err("%s: invalid index %u\n", __func__, idx);
|
||
|
|
return ERR_PTR(-EINVAL);
|
||
|
|
}
|
||
|
|
|
||
|
|
return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int rpm_clk_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct rpm_cc *rcc;
|
||
|
|
int ret;
|
||
|
|
size_t num_clks, i;
|
||
|
|
struct qcom_rpm *rpm;
|
||
|
|
struct clk_rpm **rpm_clks;
|
||
|
|
const struct rpm_clk_desc *desc;
|
||
|
|
|
||
|
|
rpm = dev_get_drvdata(pdev->dev.parent);
|
||
|
|
if (!rpm) {
|
||
|
|
dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
desc = of_device_get_match_data(&pdev->dev);
|
||
|
|
if (!desc)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
rpm_clks = desc->clks;
|
||
|
|
num_clks = desc->num_clks;
|
||
|
|
|
||
|
|
rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
|
||
|
|
if (!rcc)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
rcc->clks = rpm_clks;
|
||
|
|
rcc->num_clks = num_clks;
|
||
|
|
mutex_init(&rcc->xo_lock);
|
||
|
|
|
||
|
|
for (i = 0; i < num_clks; i++) {
|
||
|
|
if (!rpm_clks[i])
|
||
|
|
continue;
|
||
|
|
|
||
|
|
rpm_clks[i]->rpm = rpm;
|
||
|
|
rpm_clks[i]->rpm_cc = rcc;
|
||
|
|
|
||
|
|
ret = clk_rpm_handoff(rpm_clks[i]);
|
||
|
|
if (ret)
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < num_clks; i++) {
|
||
|
|
if (!rpm_clks[i])
|
||
|
|
continue;
|
||
|
|
|
||
|
|
ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
|
||
|
|
if (ret)
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = of_clk_add_hw_provider(pdev->dev.of_node, qcom_rpm_clk_hw_get,
|
||
|
|
rcc);
|
||
|
|
if (ret)
|
||
|
|
goto err;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
err:
|
||
|
|
dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int rpm_clk_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
of_clk_del_provider(pdev->dev.of_node);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver rpm_clk_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "qcom-clk-rpm",
|
||
|
|
.of_match_table = rpm_clk_match_table,
|
||
|
|
},
|
||
|
|
.probe = rpm_clk_probe,
|
||
|
|
.remove = rpm_clk_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init rpm_clk_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&rpm_clk_driver);
|
||
|
|
}
|
||
|
|
core_initcall(rpm_clk_init);
|
||
|
|
|
||
|
|
static void __exit rpm_clk_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&rpm_clk_driver);
|
||
|
|
}
|
||
|
|
module_exit(rpm_clk_exit);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|
||
|
|
MODULE_ALIAS("platform:qcom-clk-rpm");
|