522 lines
12 KiB
C
522 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
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#include "common.h"
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "reset.h"
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#include "gdsc.h"
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#define CX_GMU_CBCR_SLEEP_MASK 0xF
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#define CX_GMU_CBCR_SLEEP_SHIFT 4
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#define CX_GMU_CBCR_WAKE_MASK 0xF
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#define CX_GMU_CBCR_WAKE_SHIFT 8
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enum {
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P_BI_TCXO,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL0_OUT_ODD,
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P_GPU_CC_PLL1_OUT_EVEN,
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P_GPU_CC_PLL1_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_ODD,
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P_CRC_DIV,
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};
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static const struct pll_vco fabia_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 506MHz Configuration*/
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static const struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x1A,
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.alpha = 0x5AAA,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002067,
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.test_ctl_val = 0x40000000,
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.test_ctl_hi_val = 0x00000002,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00004805,
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};
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static struct clk_alpha_pll gpu_cc_pll0 = {
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.offset = 0x0,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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},
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};
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static struct clk_fixed_factor crc_div = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "crc_div",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_fixed_factor_ops,
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},
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};
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/* 514MHz Configuration*/
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static const struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x1A,
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.alpha = 0xC555,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002067,
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.test_ctl_val = 0x40000000,
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.test_ctl_hi_val = 0x00000002,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00004805,
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};
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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},
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .fw_name = "gcc_gpu_gpll0_clk" },
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{ .fw_name = "gcc_gpu_gpll0_div_clk" },
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};
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_CRC_DIV, 1 },
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{ P_GPU_CC_PLL0_OUT_ODD, 2 },
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{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
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{ P_GPU_CC_PLL1_OUT_ODD, 4 },
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{ P_GPLL0_OUT_MAIN, 5 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_1[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &crc_div.hw },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .fw_name = "gcc_gpu_gpll0_clk" },
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
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F(253000000, P_CRC_DIV, 1, 0, 0),
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F(355000000, P_CRC_DIV, 1, 0, 0),
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F(430000000, P_CRC_DIV, 1, 0, 0),
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F(565000000, P_CRC_DIV, 1, 0, 0),
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F(650000000, P_CRC_DIV, 1, 0, 0),
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F(800000000, P_CRC_DIV, 1, 0, 0),
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F(825000000, P_CRC_DIV, 1, 0, 0),
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F(850000000, P_CRC_DIV, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
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.cmd_rcgr = 0x101c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_1,
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.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk_src",
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch gpu_cc_acd_ahb_clk = {
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.halt_reg = 0x1168,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1168,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_acd_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_acd_cxo_clk = {
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.halt_reg = 0x1164,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1164,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_acd_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gfx3d_clk = {
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.halt_reg = 0x10a4,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x10a4,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gfx3d_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
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.halt_reg = 0x10a8,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x10a8,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gfx3d_slv_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_snoc_dvm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_clk = {
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_cxo_clk = {
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.halt_reg = 0x1060,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1060,
|
||
|
|
.enable_mask = BIT(0),
|
||
|
|
.hw.init = &(struct clk_init_data){
|
||
|
|
.name = "gpu_cc_gx_cxo_clk",
|
||
|
|
.ops = &clk_branch2_ops,
|
||
|
|
},
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
|
||
|
|
.halt_reg = 0x1054,
|
||
|
|
.halt_check = BRANCH_HALT_SKIP,
|
||
|
|
.clkr = {
|
||
|
|
.enable_reg = 0x1054,
|
||
|
|
.enable_mask = BIT(0),
|
||
|
|
.hw.init = &(struct clk_init_data){
|
||
|
|
.name = "gpu_cc_gx_gfx3d_clk",
|
||
|
|
.parent_hws = (const struct clk_hw*[]){
|
||
|
|
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||
|
|
},
|
||
|
|
.num_parents = 1,
|
||
|
|
.flags = CLK_SET_RATE_PARENT,
|
||
|
|
.ops = &clk_branch2_ops,
|
||
|
|
},
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
||
|
|
.halt_reg = 0x1064,
|
||
|
|
.halt_check = BRANCH_HALT,
|
||
|
|
.clkr = {
|
||
|
|
.enable_reg = 0x1064,
|
||
|
|
.enable_mask = BIT(0),
|
||
|
|
.hw.init = &(struct clk_init_data){
|
||
|
|
.name = "gpu_cc_gx_gmu_clk",
|
||
|
|
.parent_hws = (const struct clk_hw*[]){
|
||
|
|
&gpu_cc_gmu_clk_src.clkr.hw,
|
||
|
|
},
|
||
|
|
.num_parents = 1,
|
||
|
|
.flags = CLK_SET_RATE_PARENT,
|
||
|
|
.ops = &clk_branch2_ops,
|
||
|
|
},
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_branch gpu_cc_gx_vsense_clk = {
|
||
|
|
.halt_reg = 0x1058,
|
||
|
|
.halt_check = BRANCH_HALT_DELAY,
|
||
|
|
.clkr = {
|
||
|
|
.enable_reg = 0x1058,
|
||
|
|
.enable_mask = BIT(0),
|
||
|
|
.hw.init = &(struct clk_init_data){
|
||
|
|
.name = "gpu_cc_gx_vsense_clk",
|
||
|
|
.ops = &clk_branch2_ops,
|
||
|
|
},
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct gdsc gpu_cx_gdsc = {
|
||
|
|
.gdscr = 0x106c,
|
||
|
|
.gds_hw_ctrl = 0x1540,
|
||
|
|
.pd = {
|
||
|
|
.name = "gpu_cx_gdsc",
|
||
|
|
},
|
||
|
|
.pwrsts = PWRSTS_OFF_ON,
|
||
|
|
.flags = VOTABLE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct gdsc gpu_gx_gdsc = {
|
||
|
|
.gdscr = 0x100c,
|
||
|
|
.clamp_io_ctrl = 0x1508,
|
||
|
|
.pd = {
|
||
|
|
.name = "gpu_gx_gdsc",
|
||
|
|
.power_on = gdsc_gx_do_nothing_enable,
|
||
|
|
},
|
||
|
|
.pwrsts = PWRSTS_OFF_ON,
|
||
|
|
.flags = CLAMP_IO | POLL_CFG_GDSCR,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_hw *gpu_cc_sm6350_hws[] = {
|
||
|
|
[GPU_CC_CRC_DIV] = &crc_div.hw,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_regmap *gpu_cc_sm6350_clocks[] = {
|
||
|
|
[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,
|
||
|
|
[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
|
||
|
|
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
||
|
|
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
||
|
|
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
|
||
|
|
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
|
||
|
|
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
||
|
|
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
|
||
|
|
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
|
||
|
|
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
||
|
|
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
||
|
|
[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
|
||
|
|
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
|
||
|
|
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
|
||
|
|
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
||
|
|
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
|
||
|
|
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
||
|
|
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct gdsc *gpu_cc_sm6350_gdscs[] = {
|
||
|
|
[GPU_CX_GDSC] = &gpu_cx_gdsc,
|
||
|
|
[GPU_GX_GDSC] = &gpu_gx_gdsc,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct regmap_config gpu_cc_sm6350_regmap_config = {
|
||
|
|
.reg_bits = 32,
|
||
|
|
.reg_stride = 4,
|
||
|
|
.val_bits = 32,
|
||
|
|
.max_register = 0x8008,
|
||
|
|
.fast_io = true,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct qcom_cc_desc gpu_cc_sm6350_desc = {
|
||
|
|
.config = &gpu_cc_sm6350_regmap_config,
|
||
|
|
.clk_hws = gpu_cc_sm6350_hws,
|
||
|
|
.num_clk_hws = ARRAY_SIZE(gpu_cc_sm6350_hws),
|
||
|
|
.clks = gpu_cc_sm6350_clocks,
|
||
|
|
.num_clks = ARRAY_SIZE(gpu_cc_sm6350_clocks),
|
||
|
|
.gdscs = gpu_cc_sm6350_gdscs,
|
||
|
|
.num_gdscs = ARRAY_SIZE(gpu_cc_sm6350_gdscs),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id gpu_cc_sm6350_match_table[] = {
|
||
|
|
{ .compatible = "qcom,sm6350-gpucc" },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, gpu_cc_sm6350_match_table);
|
||
|
|
|
||
|
|
static int gpu_cc_sm6350_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct regmap *regmap;
|
||
|
|
unsigned int value, mask;
|
||
|
|
|
||
|
|
regmap = qcom_cc_map(pdev, &gpu_cc_sm6350_desc);
|
||
|
|
if (IS_ERR(regmap))
|
||
|
|
return PTR_ERR(regmap);
|
||
|
|
|
||
|
|
clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
||
|
|
clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
||
|
|
|
||
|
|
/* Configure gpu_cc_cx_gmu_clk with recommended wakeup/sleep settings */
|
||
|
|
mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
|
||
|
|
mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
|
||
|
|
value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
|
||
|
|
regmap_update_bits(regmap, 0x1098, mask, value);
|
||
|
|
|
||
|
|
return qcom_cc_really_probe(pdev, &gpu_cc_sm6350_desc, regmap);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver gpu_cc_sm6350_driver = {
|
||
|
|
.probe = gpu_cc_sm6350_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "sm6350-gpucc",
|
||
|
|
.of_match_table = gpu_cc_sm6350_match_table,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init gpu_cc_sm6350_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&gpu_cc_sm6350_driver);
|
||
|
|
}
|
||
|
|
core_initcall(gpu_cc_sm6350_init);
|
||
|
|
|
||
|
|
static void __exit gpu_cc_sm6350_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&gpu_cc_sm6350_driver);
|
||
|
|
}
|
||
|
|
module_exit(gpu_cc_sm6350_exit);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("QTI GPU_CC LAGOON Driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|