56 lines
1.0 KiB
C
56 lines
1.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2016 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*/
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#ifndef _CCU_SUN8I_A83T_H_
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#define _CCU_SUN8I_A83T_H_
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#include <dt-bindings/clock/sun8i-a83t-ccu.h>
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#include <dt-bindings/reset/sun8i-a83t-ccu.h>
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#define CLK_PLL_C0CPUX 0
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#define CLK_PLL_C1CPUX 1
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#define CLK_PLL_AUDIO 2
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#define CLK_PLL_VIDEO0 3
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#define CLK_PLL_VE 4
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#define CLK_PLL_DDR 5
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/* pll-periph is exported to the PRCM block */
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#define CLK_PLL_GPU 7
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#define CLK_PLL_HSIC 8
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/* pll-de is exported for the display engine */
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#define CLK_PLL_VIDEO1 10
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/* The CPUX clocks are exported */
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#define CLK_AXI0 13
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#define CLK_AXI1 14
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#define CLK_AHB1 15
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#define CLK_AHB2 16
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#define CLK_APB1 17
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#define CLK_APB2 18
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/* bus gates exported */
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#define CLK_CCI400 58
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/* module and usb clocks exported */
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#define CLK_DRAM 82
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/* dram gates and more module clocks exported */
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#define CLK_MBUS 95
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/* more module clocks exported */
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#define CLK_NUMBER (CLK_GPU_HYD + 1)
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#endif /* _CCU_SUN8I_A83T_H_ */
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