356 lines
7.7 KiB
C
356 lines
7.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Freescale FlexTimer Module (FTM) timer driver.
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include <linux/fsl/ftm.h>
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#define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_MASK_SHIFT)
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struct ftm_clock_device {
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void __iomem *clksrc_base;
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void __iomem *clkevt_base;
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unsigned long periodic_cyc;
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unsigned long ps;
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bool big_endian;
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};
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static struct ftm_clock_device *priv;
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static inline u32 ftm_readl(void __iomem *addr)
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{
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if (priv->big_endian)
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return ioread32be(addr);
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else
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return ioread32(addr);
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}
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static inline void ftm_writel(u32 val, void __iomem *addr)
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{
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if (priv->big_endian)
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iowrite32be(val, addr);
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else
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iowrite32(val, addr);
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}
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static inline void ftm_counter_enable(void __iomem *base)
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{
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u32 val;
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/* select and enable counter clock source */
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val = ftm_readl(base + FTM_SC);
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val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
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val |= priv->ps | FTM_SC_CLK(1);
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ftm_writel(val, base + FTM_SC);
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}
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static inline void ftm_counter_disable(void __iomem *base)
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{
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u32 val;
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/* disable counter clock source */
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val = ftm_readl(base + FTM_SC);
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val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
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ftm_writel(val, base + FTM_SC);
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}
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static inline void ftm_irq_acknowledge(void __iomem *base)
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{
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u32 val;
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val = ftm_readl(base + FTM_SC);
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val &= ~FTM_SC_TOF;
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ftm_writel(val, base + FTM_SC);
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}
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static inline void ftm_irq_enable(void __iomem *base)
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{
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u32 val;
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val = ftm_readl(base + FTM_SC);
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val |= FTM_SC_TOIE;
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ftm_writel(val, base + FTM_SC);
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}
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static inline void ftm_irq_disable(void __iomem *base)
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{
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u32 val;
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val = ftm_readl(base + FTM_SC);
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val &= ~FTM_SC_TOIE;
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ftm_writel(val, base + FTM_SC);
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}
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static inline void ftm_reset_counter(void __iomem *base)
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{
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/*
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* The CNT register contains the FTM counter value.
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* Reset clears the CNT register. Writing any value to COUNT
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* updates the counter with its initial value, CNTIN.
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*/
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ftm_writel(0x00, base + FTM_CNT);
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}
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static u64 notrace ftm_read_sched_clock(void)
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{
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return ftm_readl(priv->clksrc_base + FTM_CNT);
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}
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static int ftm_set_next_event(unsigned long delta,
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struct clock_event_device *unused)
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{
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/*
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* The CNNIN and MOD are all double buffer registers, writing
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* to the MOD register latches the value into a buffer. The MOD
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* register is updated with the value of its write buffer with
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* the following scenario:
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* a, the counter source clock is disabled.
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*/
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ftm_counter_disable(priv->clkevt_base);
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/* Force the value of CNTIN to be loaded into the FTM counter */
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ftm_reset_counter(priv->clkevt_base);
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/*
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* The counter increments until the value of MOD is reached,
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* at which point the counter is reloaded with the value of CNTIN.
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* The TOF (the overflow flag) bit is set when the FTM counter
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* changes from MOD to CNTIN. So we should using the delta - 1.
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*/
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ftm_writel(delta - 1, priv->clkevt_base + FTM_MOD);
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ftm_counter_enable(priv->clkevt_base);
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ftm_irq_enable(priv->clkevt_base);
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return 0;
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}
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static int ftm_set_oneshot(struct clock_event_device *evt)
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{
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ftm_counter_disable(priv->clkevt_base);
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return 0;
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}
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static int ftm_set_periodic(struct clock_event_device *evt)
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{
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ftm_set_next_event(priv->periodic_cyc, evt);
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return 0;
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}
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static irqreturn_t ftm_evt_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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ftm_irq_acknowledge(priv->clkevt_base);
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if (likely(clockevent_state_oneshot(evt))) {
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ftm_irq_disable(priv->clkevt_base);
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ftm_counter_disable(priv->clkevt_base);
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}
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct clock_event_device ftm_clockevent = {
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.name = "Freescale ftm timer",
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_state_periodic = ftm_set_periodic,
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.set_state_oneshot = ftm_set_oneshot,
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.set_next_event = ftm_set_next_event,
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.rating = 300,
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};
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static int __init ftm_clockevent_init(unsigned long freq, int irq)
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{
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int err;
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ftm_writel(0x00, priv->clkevt_base + FTM_CNTIN);
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ftm_writel(~0u, priv->clkevt_base + FTM_MOD);
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ftm_reset_counter(priv->clkevt_base);
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err = request_irq(irq, ftm_evt_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
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"Freescale ftm timer", &ftm_clockevent);
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if (err) {
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pr_err("ftm: setup irq failed: %d\n", err);
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return err;
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}
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ftm_clockevent.cpumask = cpumask_of(0);
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ftm_clockevent.irq = irq;
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clockevents_config_and_register(&ftm_clockevent,
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freq / (1 << priv->ps),
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1, 0xffff);
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ftm_counter_enable(priv->clkevt_base);
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return 0;
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}
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static int __init ftm_clocksource_init(unsigned long freq)
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{
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int err;
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ftm_writel(0x00, priv->clksrc_base + FTM_CNTIN);
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ftm_writel(~0u, priv->clksrc_base + FTM_MOD);
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ftm_reset_counter(priv->clksrc_base);
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sched_clock_register(ftm_read_sched_clock, 16, freq / (1 << priv->ps));
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err = clocksource_mmio_init(priv->clksrc_base + FTM_CNT, "fsl-ftm",
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freq / (1 << priv->ps), 300, 16,
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clocksource_mmio_readl_up);
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if (err) {
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pr_err("ftm: init clock source mmio failed: %d\n", err);
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return err;
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}
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ftm_counter_enable(priv->clksrc_base);
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return 0;
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}
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static int __init __ftm_clk_init(struct device_node *np, char *cnt_name,
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char *ftm_name)
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{
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struct clk *clk;
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int err;
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clk = of_clk_get_by_name(np, cnt_name);
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if (IS_ERR(clk)) {
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pr_err("ftm: Cannot get \"%s\": %ld\n", cnt_name, PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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err = clk_prepare_enable(clk);
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if (err) {
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pr_err("ftm: clock failed to prepare+enable \"%s\": %d\n",
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cnt_name, err);
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return err;
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}
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clk = of_clk_get_by_name(np, ftm_name);
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if (IS_ERR(clk)) {
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pr_err("ftm: Cannot get \"%s\": %ld\n", ftm_name, PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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err = clk_prepare_enable(clk);
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if (err)
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pr_err("ftm: clock failed to prepare+enable \"%s\": %d\n",
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ftm_name, err);
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return clk_get_rate(clk);
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}
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static unsigned long __init ftm_clk_init(struct device_node *np)
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{
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long freq;
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freq = __ftm_clk_init(np, "ftm-evt-counter-en", "ftm-evt");
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if (freq <= 0)
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return 0;
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freq = __ftm_clk_init(np, "ftm-src-counter-en", "ftm-src");
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if (freq <= 0)
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return 0;
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return freq;
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}
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static int __init ftm_calc_closest_round_cyc(unsigned long freq)
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{
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priv->ps = 0;
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/* The counter register is only using the lower 16 bits, and
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* if the 'freq' value is to big here, then the periodic_cyc
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* may exceed 0xFFFF.
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*/
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do {
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priv->periodic_cyc = DIV_ROUND_CLOSEST(freq,
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HZ * (1 << priv->ps++));
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} while (priv->periodic_cyc > 0xFFFF);
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if (priv->ps > FTM_PS_MAX) {
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pr_err("ftm: the prescaler is %lu > %d\n",
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priv->ps, FTM_PS_MAX);
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return -EINVAL;
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}
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return 0;
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}
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static int __init ftm_timer_init(struct device_node *np)
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{
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unsigned long freq;
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int ret, irq;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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ret = -ENXIO;
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priv->clkevt_base = of_iomap(np, 0);
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if (!priv->clkevt_base) {
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pr_err("ftm: unable to map event timer registers\n");
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goto err_clkevt;
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}
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priv->clksrc_base = of_iomap(np, 1);
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if (!priv->clksrc_base) {
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pr_err("ftm: unable to map source timer registers\n");
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goto err_clksrc;
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}
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ret = -EINVAL;
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irq = irq_of_parse_and_map(np, 0);
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if (irq <= 0) {
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pr_err("ftm: unable to get IRQ from DT, %d\n", irq);
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goto err;
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}
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priv->big_endian = of_property_read_bool(np, "big-endian");
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freq = ftm_clk_init(np);
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if (!freq)
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goto err;
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ret = ftm_calc_closest_round_cyc(freq);
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if (ret)
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goto err;
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ret = ftm_clocksource_init(freq);
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if (ret)
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goto err;
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ret = ftm_clockevent_init(freq, irq);
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if (ret)
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goto err;
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return 0;
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err:
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iounmap(priv->clksrc_base);
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err_clksrc:
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iounmap(priv->clkevt_base);
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err_clkevt:
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kfree(priv);
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return ret;
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}
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TIMER_OF_DECLARE(flextimer, "fsl,ftm-timer", ftm_timer_init);
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