576 lines
15 KiB
C
576 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2016 Cavium, Inc.
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*/
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#include "cptvf.h"
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#include "cptvf_algs.h"
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#include "request_manager.h"
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/**
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* get_free_pending_entry - get free entry from pending queue
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* @q: pending queue
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* @qlen: queue length
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*/
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static struct pending_entry *get_free_pending_entry(struct pending_queue *q,
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int qlen)
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{
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struct pending_entry *ent = NULL;
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ent = &q->head[q->rear];
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if (unlikely(ent->busy)) {
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ent = NULL;
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goto no_free_entry;
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}
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q->rear++;
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if (unlikely(q->rear == qlen))
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q->rear = 0;
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no_free_entry:
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return ent;
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}
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static inline void pending_queue_inc_front(struct pending_qinfo *pqinfo,
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int qno)
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{
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struct pending_queue *queue = &pqinfo->queue[qno];
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queue->front++;
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if (unlikely(queue->front == pqinfo->qlen))
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queue->front = 0;
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}
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static int setup_sgio_components(struct cpt_vf *cptvf, struct buf_ptr *list,
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int buf_count, u8 *buffer)
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{
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int ret = 0, i, j;
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int components;
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struct sglist_component *sg_ptr = NULL;
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struct pci_dev *pdev = cptvf->pdev;
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if (unlikely(!list)) {
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dev_err(&pdev->dev, "Input List pointer is NULL\n");
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return -EFAULT;
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}
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for (i = 0; i < buf_count; i++) {
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if (likely(list[i].vptr)) {
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list[i].dma_addr = dma_map_single(&pdev->dev,
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list[i].vptr,
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list[i].size,
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DMA_BIDIRECTIONAL);
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if (unlikely(dma_mapping_error(&pdev->dev,
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list[i].dma_addr))) {
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dev_err(&pdev->dev, "DMA map kernel buffer failed for component: %d\n",
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i);
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ret = -EIO;
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goto sg_cleanup;
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}
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}
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}
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components = buf_count / 4;
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sg_ptr = (struct sglist_component *)buffer;
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for (i = 0; i < components; i++) {
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sg_ptr->u.s.len0 = cpu_to_be16(list[i * 4 + 0].size);
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sg_ptr->u.s.len1 = cpu_to_be16(list[i * 4 + 1].size);
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sg_ptr->u.s.len2 = cpu_to_be16(list[i * 4 + 2].size);
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sg_ptr->u.s.len3 = cpu_to_be16(list[i * 4 + 3].size);
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sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);
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sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);
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sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);
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sg_ptr->ptr3 = cpu_to_be64(list[i * 4 + 3].dma_addr);
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sg_ptr++;
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}
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components = buf_count % 4;
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switch (components) {
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case 3:
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sg_ptr->u.s.len2 = cpu_to_be16(list[i * 4 + 2].size);
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sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);
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fallthrough;
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case 2:
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sg_ptr->u.s.len1 = cpu_to_be16(list[i * 4 + 1].size);
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sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);
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fallthrough;
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case 1:
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sg_ptr->u.s.len0 = cpu_to_be16(list[i * 4 + 0].size);
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sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);
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break;
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default:
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break;
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}
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return ret;
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sg_cleanup:
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for (j = 0; j < i; j++) {
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if (list[j].dma_addr) {
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dma_unmap_single(&pdev->dev, list[i].dma_addr,
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list[i].size, DMA_BIDIRECTIONAL);
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}
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list[j].dma_addr = 0;
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}
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return ret;
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}
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static inline int setup_sgio_list(struct cpt_vf *cptvf,
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struct cpt_info_buffer *info,
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struct cpt_request_info *req)
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{
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u16 g_sz_bytes = 0, s_sz_bytes = 0;
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int ret = 0;
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struct pci_dev *pdev = cptvf->pdev;
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if (req->incnt > MAX_SG_IN_CNT || req->outcnt > MAX_SG_OUT_CNT) {
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dev_err(&pdev->dev, "Request SG components are higher than supported\n");
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ret = -EINVAL;
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goto scatter_gather_clean;
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}
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/* Setup gather (input) components */
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g_sz_bytes = ((req->incnt + 3) / 4) * sizeof(struct sglist_component);
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info->gather_components = kzalloc(g_sz_bytes, req->may_sleep ? GFP_KERNEL : GFP_ATOMIC);
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if (!info->gather_components) {
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ret = -ENOMEM;
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goto scatter_gather_clean;
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}
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ret = setup_sgio_components(cptvf, req->in,
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req->incnt,
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info->gather_components);
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if (ret) {
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dev_err(&pdev->dev, "Failed to setup gather list\n");
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ret = -EFAULT;
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goto scatter_gather_clean;
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}
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/* Setup scatter (output) components */
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s_sz_bytes = ((req->outcnt + 3) / 4) * sizeof(struct sglist_component);
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info->scatter_components = kzalloc(s_sz_bytes, req->may_sleep ? GFP_KERNEL : GFP_ATOMIC);
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if (!info->scatter_components) {
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ret = -ENOMEM;
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goto scatter_gather_clean;
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}
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ret = setup_sgio_components(cptvf, req->out,
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req->outcnt,
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info->scatter_components);
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if (ret) {
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dev_err(&pdev->dev, "Failed to setup gather list\n");
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ret = -EFAULT;
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goto scatter_gather_clean;
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}
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/* Create and initialize DPTR */
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info->dlen = g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE;
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info->in_buffer = kzalloc(info->dlen, req->may_sleep ? GFP_KERNEL : GFP_ATOMIC);
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if (!info->in_buffer) {
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ret = -ENOMEM;
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goto scatter_gather_clean;
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}
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((__be16 *)info->in_buffer)[0] = cpu_to_be16(req->outcnt);
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((__be16 *)info->in_buffer)[1] = cpu_to_be16(req->incnt);
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((__be16 *)info->in_buffer)[2] = 0;
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((__be16 *)info->in_buffer)[3] = 0;
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memcpy(&info->in_buffer[8], info->gather_components,
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g_sz_bytes);
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memcpy(&info->in_buffer[8 + g_sz_bytes],
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info->scatter_components, s_sz_bytes);
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info->dptr_baddr = dma_map_single(&pdev->dev,
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(void *)info->in_buffer,
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info->dlen,
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DMA_BIDIRECTIONAL);
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if (dma_mapping_error(&pdev->dev, info->dptr_baddr)) {
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dev_err(&pdev->dev, "Mapping DPTR Failed %d\n", info->dlen);
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ret = -EIO;
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goto scatter_gather_clean;
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}
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/* Create and initialize RPTR */
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info->out_buffer = kzalloc(COMPLETION_CODE_SIZE, req->may_sleep ? GFP_KERNEL : GFP_ATOMIC);
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if (!info->out_buffer) {
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ret = -ENOMEM;
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goto scatter_gather_clean;
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}
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*((u64 *)info->out_buffer) = ~((u64)COMPLETION_CODE_INIT);
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info->alternate_caddr = (u64 *)info->out_buffer;
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info->rptr_baddr = dma_map_single(&pdev->dev,
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(void *)info->out_buffer,
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COMPLETION_CODE_SIZE,
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DMA_BIDIRECTIONAL);
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if (dma_mapping_error(&pdev->dev, info->rptr_baddr)) {
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dev_err(&pdev->dev, "Mapping RPTR Failed %d\n",
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COMPLETION_CODE_SIZE);
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ret = -EIO;
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goto scatter_gather_clean;
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}
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return 0;
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scatter_gather_clean:
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return ret;
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}
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static int send_cpt_command(struct cpt_vf *cptvf, union cpt_inst_s *cmd,
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u32 qno)
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{
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struct pci_dev *pdev = cptvf->pdev;
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struct command_qinfo *qinfo = NULL;
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struct command_queue *queue;
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struct command_chunk *chunk;
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u8 *ent;
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int ret = 0;
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if (unlikely(qno >= cptvf->nr_queues)) {
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dev_err(&pdev->dev, "Invalid queue (qno: %d, nr_queues: %d)\n",
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qno, cptvf->nr_queues);
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return -EINVAL;
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}
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qinfo = &cptvf->cqinfo;
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queue = &qinfo->queue[qno];
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/* lock commad queue */
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spin_lock(&queue->lock);
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ent = &queue->qhead->head[queue->idx * qinfo->cmd_size];
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memcpy(ent, (void *)cmd, qinfo->cmd_size);
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if (++queue->idx >= queue->qhead->size / 64) {
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hlist_for_each_entry(chunk, &queue->chead, nextchunk) {
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if (chunk == queue->qhead) {
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continue;
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} else {
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queue->qhead = chunk;
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break;
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}
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}
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queue->idx = 0;
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}
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/* make sure all memory stores are done before ringing doorbell */
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smp_wmb();
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cptvf_write_vq_doorbell(cptvf, 1);
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/* unlock command queue */
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spin_unlock(&queue->lock);
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return ret;
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}
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static void do_request_cleanup(struct cpt_vf *cptvf,
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struct cpt_info_buffer *info)
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{
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int i;
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struct pci_dev *pdev = cptvf->pdev;
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struct cpt_request_info *req;
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if (info->dptr_baddr)
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dma_unmap_single(&pdev->dev, info->dptr_baddr,
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info->dlen, DMA_BIDIRECTIONAL);
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if (info->rptr_baddr)
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dma_unmap_single(&pdev->dev, info->rptr_baddr,
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COMPLETION_CODE_SIZE, DMA_BIDIRECTIONAL);
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if (info->comp_baddr)
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dma_unmap_single(&pdev->dev, info->comp_baddr,
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sizeof(union cpt_res_s), DMA_BIDIRECTIONAL);
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if (info->req) {
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req = info->req;
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for (i = 0; i < req->outcnt; i++) {
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if (req->out[i].dma_addr)
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dma_unmap_single(&pdev->dev,
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req->out[i].dma_addr,
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req->out[i].size,
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DMA_BIDIRECTIONAL);
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}
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for (i = 0; i < req->incnt; i++) {
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if (req->in[i].dma_addr)
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dma_unmap_single(&pdev->dev,
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req->in[i].dma_addr,
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req->in[i].size,
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DMA_BIDIRECTIONAL);
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}
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}
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kfree_sensitive(info->scatter_components);
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kfree_sensitive(info->gather_components);
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kfree_sensitive(info->out_buffer);
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kfree_sensitive(info->in_buffer);
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kfree_sensitive((void *)info->completion_addr);
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kfree_sensitive(info);
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}
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static void do_post_process(struct cpt_vf *cptvf, struct cpt_info_buffer *info)
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{
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struct pci_dev *pdev = cptvf->pdev;
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if (!info) {
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dev_err(&pdev->dev, "incorrect cpt_info_buffer for post processing\n");
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return;
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}
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do_request_cleanup(cptvf, info);
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}
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static inline void process_pending_queue(struct cpt_vf *cptvf,
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struct pending_qinfo *pqinfo,
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int qno)
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{
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struct pci_dev *pdev = cptvf->pdev;
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struct pending_queue *pqueue = &pqinfo->queue[qno];
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struct pending_entry *pentry = NULL;
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struct cpt_info_buffer *info = NULL;
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union cpt_res_s *status = NULL;
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unsigned char ccode;
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while (1) {
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spin_lock_bh(&pqueue->lock);
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pentry = &pqueue->head[pqueue->front];
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if (unlikely(!pentry->busy)) {
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spin_unlock_bh(&pqueue->lock);
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break;
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}
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info = (struct cpt_info_buffer *)pentry->post_arg;
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if (unlikely(!info)) {
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dev_err(&pdev->dev, "Pending Entry post arg NULL\n");
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pending_queue_inc_front(pqinfo, qno);
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spin_unlock_bh(&pqueue->lock);
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continue;
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}
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status = (union cpt_res_s *)pentry->completion_addr;
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ccode = status->s.compcode;
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if ((status->s.compcode == CPT_COMP_E_FAULT) ||
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(status->s.compcode == CPT_COMP_E_SWERR)) {
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dev_err(&pdev->dev, "Request failed with %s\n",
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(status->s.compcode == CPT_COMP_E_FAULT) ?
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"DMA Fault" : "Software error");
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pentry->completion_addr = NULL;
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pentry->busy = false;
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||
|
|
atomic64_dec((&pqueue->pending_count));
|
||
|
|
pentry->post_arg = NULL;
|
||
|
|
pending_queue_inc_front(pqinfo, qno);
|
||
|
|
do_request_cleanup(cptvf, info);
|
||
|
|
spin_unlock_bh(&pqueue->lock);
|
||
|
|
break;
|
||
|
|
} else if (status->s.compcode == COMPLETION_CODE_INIT) {
|
||
|
|
/* check for timeout */
|
||
|
|
if (time_after_eq(jiffies,
|
||
|
|
(info->time_in +
|
||
|
|
(CPT_COMMAND_TIMEOUT * HZ)))) {
|
||
|
|
dev_err(&pdev->dev, "Request timed out");
|
||
|
|
pentry->completion_addr = NULL;
|
||
|
|
pentry->busy = false;
|
||
|
|
atomic64_dec((&pqueue->pending_count));
|
||
|
|
pentry->post_arg = NULL;
|
||
|
|
pending_queue_inc_front(pqinfo, qno);
|
||
|
|
do_request_cleanup(cptvf, info);
|
||
|
|
spin_unlock_bh(&pqueue->lock);
|
||
|
|
break;
|
||
|
|
} else if ((*info->alternate_caddr ==
|
||
|
|
(~COMPLETION_CODE_INIT)) &&
|
||
|
|
(info->extra_time < TIME_IN_RESET_COUNT)) {
|
||
|
|
info->time_in = jiffies;
|
||
|
|
info->extra_time++;
|
||
|
|
spin_unlock_bh(&pqueue->lock);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
pentry->completion_addr = NULL;
|
||
|
|
pentry->busy = false;
|
||
|
|
pentry->post_arg = NULL;
|
||
|
|
atomic64_dec((&pqueue->pending_count));
|
||
|
|
pending_queue_inc_front(pqinfo, qno);
|
||
|
|
spin_unlock_bh(&pqueue->lock);
|
||
|
|
|
||
|
|
do_post_process(info->cptvf, info);
|
||
|
|
/*
|
||
|
|
* Calling callback after we find
|
||
|
|
* that the request has been serviced
|
||
|
|
*/
|
||
|
|
pentry->callback(ccode, pentry->callback_arg);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int process_request(struct cpt_vf *cptvf, struct cpt_request_info *req)
|
||
|
|
{
|
||
|
|
int ret = 0, clear = 0, queue = 0;
|
||
|
|
struct cpt_info_buffer *info = NULL;
|
||
|
|
struct cptvf_request *cpt_req = NULL;
|
||
|
|
union ctrl_info *ctrl = NULL;
|
||
|
|
union cpt_res_s *result = NULL;
|
||
|
|
struct pending_entry *pentry = NULL;
|
||
|
|
struct pending_queue *pqueue = NULL;
|
||
|
|
struct pci_dev *pdev = cptvf->pdev;
|
||
|
|
u8 group = 0;
|
||
|
|
struct cpt_vq_command vq_cmd;
|
||
|
|
union cpt_inst_s cptinst;
|
||
|
|
|
||
|
|
info = kzalloc(sizeof(*info), req->may_sleep ? GFP_KERNEL : GFP_ATOMIC);
|
||
|
|
if (unlikely(!info)) {
|
||
|
|
dev_err(&pdev->dev, "Unable to allocate memory for info_buffer\n");
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
cpt_req = (struct cptvf_request *)&req->req;
|
||
|
|
ctrl = (union ctrl_info *)&req->ctrl;
|
||
|
|
|
||
|
|
info->cptvf = cptvf;
|
||
|
|
group = ctrl->s.grp;
|
||
|
|
ret = setup_sgio_list(cptvf, info, req);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(&pdev->dev, "Setting up SG list failed");
|
||
|
|
goto request_cleanup;
|
||
|
|
}
|
||
|
|
|
||
|
|
cpt_req->dlen = info->dlen;
|
||
|
|
/*
|
||
|
|
* Get buffer for union cpt_res_s response
|
||
|
|
* structure and its physical address
|
||
|
|
*/
|
||
|
|
info->completion_addr = kzalloc(sizeof(union cpt_res_s), req->may_sleep ? GFP_KERNEL : GFP_ATOMIC);
|
||
|
|
if (unlikely(!info->completion_addr)) {
|
||
|
|
dev_err(&pdev->dev, "Unable to allocate memory for completion_addr\n");
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto request_cleanup;
|
||
|
|
}
|
||
|
|
|
||
|
|
result = (union cpt_res_s *)info->completion_addr;
|
||
|
|
result->s.compcode = COMPLETION_CODE_INIT;
|
||
|
|
info->comp_baddr = dma_map_single(&pdev->dev,
|
||
|
|
(void *)info->completion_addr,
|
||
|
|
sizeof(union cpt_res_s),
|
||
|
|
DMA_BIDIRECTIONAL);
|
||
|
|
if (dma_mapping_error(&pdev->dev, info->comp_baddr)) {
|
||
|
|
dev_err(&pdev->dev, "mapping compptr Failed %lu\n",
|
||
|
|
sizeof(union cpt_res_s));
|
||
|
|
ret = -EFAULT;
|
||
|
|
goto request_cleanup;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Fill the VQ command */
|
||
|
|
vq_cmd.cmd.u64 = 0;
|
||
|
|
vq_cmd.cmd.s.opcode = cpu_to_be16(cpt_req->opcode.flags);
|
||
|
|
vq_cmd.cmd.s.param1 = cpu_to_be16(cpt_req->param1);
|
||
|
|
vq_cmd.cmd.s.param2 = cpu_to_be16(cpt_req->param2);
|
||
|
|
vq_cmd.cmd.s.dlen = cpu_to_be16(cpt_req->dlen);
|
||
|
|
|
||
|
|
vq_cmd.dptr = info->dptr_baddr;
|
||
|
|
vq_cmd.rptr = info->rptr_baddr;
|
||
|
|
vq_cmd.cptr.u64 = 0;
|
||
|
|
vq_cmd.cptr.s.grp = group;
|
||
|
|
/* Get Pending Entry to submit command */
|
||
|
|
/* Always queue 0, because 1 queue per VF */
|
||
|
|
queue = 0;
|
||
|
|
pqueue = &cptvf->pqinfo.queue[queue];
|
||
|
|
|
||
|
|
if (atomic64_read(&pqueue->pending_count) > PENDING_THOLD) {
|
||
|
|
dev_err(&pdev->dev, "pending threshold reached\n");
|
||
|
|
process_pending_queue(cptvf, &cptvf->pqinfo, queue);
|
||
|
|
}
|
||
|
|
|
||
|
|
get_pending_entry:
|
||
|
|
spin_lock_bh(&pqueue->lock);
|
||
|
|
pentry = get_free_pending_entry(pqueue, cptvf->pqinfo.qlen);
|
||
|
|
if (unlikely(!pentry)) {
|
||
|
|
spin_unlock_bh(&pqueue->lock);
|
||
|
|
if (clear == 0) {
|
||
|
|
process_pending_queue(cptvf, &cptvf->pqinfo, queue);
|
||
|
|
clear = 1;
|
||
|
|
goto get_pending_entry;
|
||
|
|
}
|
||
|
|
dev_err(&pdev->dev, "Get free entry failed\n");
|
||
|
|
dev_err(&pdev->dev, "queue: %d, rear: %d, front: %d\n",
|
||
|
|
queue, pqueue->rear, pqueue->front);
|
||
|
|
ret = -EFAULT;
|
||
|
|
goto request_cleanup;
|
||
|
|
}
|
||
|
|
|
||
|
|
pentry->completion_addr = info->completion_addr;
|
||
|
|
pentry->post_arg = (void *)info;
|
||
|
|
pentry->callback = req->callback;
|
||
|
|
pentry->callback_arg = req->callback_arg;
|
||
|
|
info->pentry = pentry;
|
||
|
|
pentry->busy = true;
|
||
|
|
atomic64_inc(&pqueue->pending_count);
|
||
|
|
|
||
|
|
/* Send CPT command */
|
||
|
|
info->pentry = pentry;
|
||
|
|
info->time_in = jiffies;
|
||
|
|
info->req = req;
|
||
|
|
|
||
|
|
/* Create the CPT_INST_S type command for HW intrepretation */
|
||
|
|
cptinst.s.doneint = true;
|
||
|
|
cptinst.s.res_addr = (u64)info->comp_baddr;
|
||
|
|
cptinst.s.tag = 0;
|
||
|
|
cptinst.s.grp = 0;
|
||
|
|
cptinst.s.wq_ptr = 0;
|
||
|
|
cptinst.s.ei0 = vq_cmd.cmd.u64;
|
||
|
|
cptinst.s.ei1 = vq_cmd.dptr;
|
||
|
|
cptinst.s.ei2 = vq_cmd.rptr;
|
||
|
|
cptinst.s.ei3 = vq_cmd.cptr.u64;
|
||
|
|
|
||
|
|
ret = send_cpt_command(cptvf, &cptinst, queue);
|
||
|
|
spin_unlock_bh(&pqueue->lock);
|
||
|
|
if (unlikely(ret)) {
|
||
|
|
dev_err(&pdev->dev, "Send command failed for AE\n");
|
||
|
|
ret = -EFAULT;
|
||
|
|
goto request_cleanup;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
request_cleanup:
|
||
|
|
dev_dbg(&pdev->dev, "Failed to submit CPT command\n");
|
||
|
|
do_request_cleanup(cptvf, info);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void vq_post_process(struct cpt_vf *cptvf, u32 qno)
|
||
|
|
{
|
||
|
|
struct pci_dev *pdev = cptvf->pdev;
|
||
|
|
|
||
|
|
if (unlikely(qno > cptvf->nr_queues)) {
|
||
|
|
dev_err(&pdev->dev, "Request for post processing on invalid pending queue: %u\n",
|
||
|
|
qno);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
process_pending_queue(cptvf, &cptvf->pqinfo, qno);
|
||
|
|
}
|
||
|
|
|
||
|
|
int cptvf_do_request(void *vfdev, struct cpt_request_info *req)
|
||
|
|
{
|
||
|
|
struct cpt_vf *cptvf = (struct cpt_vf *)vfdev;
|
||
|
|
struct pci_dev *pdev = cptvf->pdev;
|
||
|
|
|
||
|
|
if (!cpt_device_ready(cptvf)) {
|
||
|
|
dev_err(&pdev->dev, "CPT Device is not ready");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((cptvf->vftype == SE_TYPES) && (!req->ctrl.s.se_req)) {
|
||
|
|
dev_err(&pdev->dev, "CPTVF-%d of SE TYPE got AE request",
|
||
|
|
cptvf->vfid);
|
||
|
|
return -EINVAL;
|
||
|
|
} else if ((cptvf->vftype == AE_TYPES) && (req->ctrl.s.se_req)) {
|
||
|
|
dev_err(&pdev->dev, "CPTVF-%d of AE TYPE got SE request",
|
||
|
|
cptvf->vfid);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return process_request(cptvf, req);
|
||
|
|
}
|