348 lines
10 KiB
C
348 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
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*
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* Copyright (C) 2021 Corentin LABBE <clabbe@baylibre.com>
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*
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* General notes on this driver:
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* Called either Crypto Acceleration Engine Module, Security Acceleration Engine
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* or IPSEC module in the datasheet, it will be called Crypto Engine for short
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* in this driver.
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* The CE was designed to handle IPSEC and wifi(TKIP WEP) protocol.
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* It can handle AES, DES, 3DES, MD5, WEP, TKIP, SHA1, HMAC(MD5), HMAC(SHA1),
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* Michael cipher/digest suites.
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* It acts the same as a network hw, with both RX and TX chained descriptors.
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*/
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#include <crypto/aes.h>
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#include <crypto/engine.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/skcipher.h>
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#include <linux/crypto.h>
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#include <linux/debugfs.h>
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#include <linux/hw_random.h>
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#define TQ0_TYPE_DATA 0
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#define TQ0_TYPE_CTRL BIT(0)
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#define TQ1_CIPHER BIT(1)
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#define TQ2_AUTH BIT(2)
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#define TQ3_IV BIT(3)
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#define TQ4_KEY0 BIT(4)
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#define TQ5_KEY4 BIT(5)
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#define TQ6_KEY6 BIT(6)
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#define TQ7_AKEY0 BIT(7)
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#define TQ8_AKEY2 BIT(8)
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#define TQ9_AKEY2 BIT(9)
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#define ECB_AES 0x2
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#define DESC_LAST 0x01
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#define DESC_FIRST 0x02
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#define IPSEC_ID 0x0000
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#define IPSEC_STATUS_REG 0x00a8
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#define IPSEC_RAND_NUM_REG 0x00ac
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#define IPSEC_DMA_DEVICE_ID 0xff00
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#define IPSEC_DMA_STATUS 0xff04
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#define IPSEC_TXDMA_CTRL 0xff08
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#define IPSEC_TXDMA_FIRST_DESC 0xff0c
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#define IPSEC_TXDMA_CURR_DESC 0xff10
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#define IPSEC_RXDMA_CTRL 0xff14
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#define IPSEC_RXDMA_FIRST_DESC 0xff18
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#define IPSEC_RXDMA_CURR_DESC 0xff1c
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#define IPSEC_TXDMA_BUF_ADDR 0xff28
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#define IPSEC_RXDMA_BUF_ADDR 0xff38
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#define IPSEC_RXDMA_BUF_SIZE 0xff30
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#define CE_ENCRYPTION 0x01
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#define CE_DECRYPTION 0x03
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#define MAXDESC 6
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#define DMA_STATUS_RS_EOFI BIT(22)
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#define DMA_STATUS_RS_PERR BIT(24)
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#define DMA_STATUS_RS_DERR BIT(25)
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#define DMA_STATUS_TS_EOFI BIT(27)
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#define DMA_STATUS_TS_PERR BIT(29)
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#define DMA_STATUS_TS_DERR BIT(30)
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#define TXDMA_CTRL_START BIT(31)
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#define TXDMA_CTRL_CONTINUE BIT(30)
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#define TXDMA_CTRL_CHAIN_MODE BIT(29)
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/* the burst value is not documented in the datasheet */
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#define TXDMA_CTRL_BURST_UNK BIT(22)
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#define TXDMA_CTRL_INT_FAIL BIT(17)
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#define TXDMA_CTRL_INT_PERR BIT(16)
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#define RXDMA_CTRL_START BIT(31)
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#define RXDMA_CTRL_CONTINUE BIT(30)
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#define RXDMA_CTRL_CHAIN_MODE BIT(29)
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/* the burst value is not documented in the datasheet */
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#define RXDMA_CTRL_BURST_UNK BIT(22)
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#define RXDMA_CTRL_INT_FINISH BIT(18)
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#define RXDMA_CTRL_INT_FAIL BIT(17)
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#define RXDMA_CTRL_INT_PERR BIT(16)
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#define RXDMA_CTRL_INT_EOD BIT(15)
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#define RXDMA_CTRL_INT_EOF BIT(14)
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#define CE_CPU 0
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#define CE_DMA 1
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/*
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* struct sl3516_ce_descriptor - descriptor for CE operations
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* @frame_ctrl: Information for the current descriptor
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* @flag_status: For send packet, describe flag of operations.
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* @buf_adr: pointer to a send/recv buffer for data packet
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* @next_desc: control linking to other descriptors
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*/
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struct descriptor {
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union {
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u32 raw;
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/*
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* struct desc_frame_ctrl - Information for the current descriptor
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* @buffer_size: the size of buffer at buf_adr
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* @desc_count: Upon completion of a DMA operation, DMA
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* write the number of descriptors used
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* for the current frame
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* @checksum: unknown
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* @authcomp: unknown
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* @perr: Protocol error during processing this descriptor
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* @derr: Data error during processing this descriptor
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* @own: 0 if owned by CPU, 1 for DMA
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*/
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struct desc_frame_ctrl {
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u32 buffer_size :16;
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u32 desc_count :6;
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u32 checksum :6;
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u32 authcomp :1;
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u32 perr :1;
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u32 derr :1;
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u32 own :1;
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} bits;
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} frame_ctrl;
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union {
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u32 raw;
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/*
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* struct desc_flag_status - flag for this descriptor
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* @tqflag: list of flag describing the type of operation
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* to be performed.
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*/
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struct desc_tx_flag_status {
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u32 tqflag :10;
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u32 unused :22;
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} tx_flag;
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} flag_status;
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u32 buf_adr;
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union {
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u32 next_descriptor;
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/*
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* struct desc_next - describe chaining of descriptors
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* @sof_eof: does the descriptor is first (0x11),
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* the last (0x01), middle of a chan (0x00)
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* or the only one (0x11)
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* @dec: AHB bus address increase (0), decrease (1)
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* @eofie: End of frame interrupt enable
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* @ndar: Next descriptor address
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*/
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struct desc_next {
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u32 sof_eof :2;
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u32 dec :1;
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u32 eofie :1;
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u32 ndar :28;
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} bits;
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} next_desc;
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};
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/*
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* struct control - The value of this register is used to set the
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* operation mode of the IPSec Module.
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* @process_id: Used to identify the process. The number will be copied
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* to the descriptor status of the received packet.
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* @auth_check_len: Number of 32-bit words to be checked or appended by the
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* authentication module
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* @auth_algorithm:
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* @auth_mode: 0:append 1:Check Authentication Result
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* @fcs_stream_copy: 0:enable 1:disable authentication stream copy
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* @mix_key_sel: 0:use rCipherKey0-3 1:use Key Mixer
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* @aesnk: AES Key Size
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* @cipher_algorithm: choice of CBC/ECE and AES/DES/3DES
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* @op_mode: Operation Mode for the IPSec Module
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*/
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struct pkt_control_header {
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u32 process_id :8;
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u32 auth_check_len :3;
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u32 un1 :1;
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u32 auth_algorithm :3;
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u32 auth_mode :1;
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u32 fcs_stream_copy :1;
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u32 un2 :2;
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u32 mix_key_sel :1;
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u32 aesnk :4;
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u32 cipher_algorithm :3;
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u32 un3 :1;
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u32 op_mode :4;
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};
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struct pkt_control_cipher {
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u32 algorithm_len :16;
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u32 header_len :16;
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};
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/*
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* struct pkt_control_ecb - control packet for ECB
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*/
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struct pkt_control_ecb {
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struct pkt_control_header control;
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struct pkt_control_cipher cipher;
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unsigned char key[AES_MAX_KEY_SIZE];
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};
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/*
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* struct sl3516_ce_dev - main container for all this driver information
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* @base: base address
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* @clks: clocks used
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* @reset: pointer to reset controller
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* @dev: the platform device
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* @engine: ptr to the crypto/crypto_engine
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* @complete: completion for the current task on this flow
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* @status: set to 1 by interrupt if task is done
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* @dtx: base DMA address for TX descriptors
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* @tx base address of TX descriptors
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* @drx: base DMA address for RX descriptors
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* @rx base address of RX descriptors
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* @ctx current used TX descriptor
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* @crx current used RX descriptor
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* @trng hw_random structure for RNG
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* @hwrng_stat_req number of HWRNG requests
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* @hwrng_stat_bytes total number of bytes generated by RNG
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* @stat_irq number of IRQ handled by CE
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* @stat_irq_tx number of TX IRQ handled by CE
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* @stat_irq_rx number of RX IRQ handled by CE
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* @stat_req number of requests handled by CE
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* @fallbak_sg_count_tx number of fallback due to destination SG count
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* @fallbak_sg_count_rx number of fallback due to source SG count
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* @fallbak_not_same_len number of fallback due to difference in SG length
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* @dbgfs_dir: Debugfs dentry for statistic directory
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* @dbgfs_stats: Debugfs dentry for statistic counters
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*/
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struct sl3516_ce_dev {
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void __iomem *base;
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struct clk *clks;
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struct reset_control *reset;
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struct device *dev;
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struct crypto_engine *engine;
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struct completion complete;
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int status;
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dma_addr_t dtx;
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struct descriptor *tx;
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dma_addr_t drx;
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struct descriptor *rx;
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int ctx;
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int crx;
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struct hwrng trng;
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unsigned long hwrng_stat_req;
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unsigned long hwrng_stat_bytes;
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unsigned long stat_irq;
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unsigned long stat_irq_tx;
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unsigned long stat_irq_rx;
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unsigned long stat_req;
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unsigned long fallback_sg_count_tx;
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unsigned long fallback_sg_count_rx;
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unsigned long fallback_not_same_len;
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unsigned long fallback_mod16;
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unsigned long fallback_align16;
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#ifdef CONFIG_CRYPTO_DEV_SL3516_DEBUG
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struct dentry *dbgfs_dir;
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struct dentry *dbgfs_stats;
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#endif
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void *pctrl;
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dma_addr_t dctrl;
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};
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struct sginfo {
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u32 addr;
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u32 len;
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};
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/*
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* struct sl3516_ce_cipher_req_ctx - context for a skcipher request
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* @t_src: list of mapped SGs with their size
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* @t_dst: list of mapped SGs with their size
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* @op_dir: direction (encrypt vs decrypt) for this request
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* @pctrllen: the length of the ctrl packet
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* @tqflag: the TQflag to set in data packet
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* @h pointer to the pkt_control_cipher header
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* @nr_sgs: number of source SG
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* @nr_sgd: number of destination SG
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* @fallback_req: request struct for invoking the fallback skcipher TFM
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*/
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struct sl3516_ce_cipher_req_ctx {
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struct sginfo t_src[MAXDESC];
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struct sginfo t_dst[MAXDESC];
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u32 op_dir;
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unsigned int pctrllen;
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u32 tqflag;
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struct pkt_control_cipher *h;
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int nr_sgs;
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int nr_sgd;
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struct skcipher_request fallback_req; // keep at the end
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};
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/*
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* struct sl3516_ce_cipher_tfm_ctx - context for a skcipher TFM
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* @enginectx: crypto_engine used by this TFM
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* @key: pointer to key data
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* @keylen: len of the key
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* @ce: pointer to the private data of driver handling this TFM
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* @fallback_tfm: pointer to the fallback TFM
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*
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* enginectx must be the first element
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*/
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struct sl3516_ce_cipher_tfm_ctx {
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struct crypto_engine_ctx enginectx;
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u32 *key;
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u32 keylen;
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struct sl3516_ce_dev *ce;
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struct crypto_skcipher *fallback_tfm;
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};
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/*
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* struct sl3516_ce_alg_template - crypto_alg template
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* @type: the CRYPTO_ALG_TYPE for this template
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* @mode: value to be used in control packet for this algorithm
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* @ce: pointer to the sl3516_ce_dev structure associated with
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* this template
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* @alg: one of sub struct must be used
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* @stat_req: number of request done on this template
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* @stat_fb: number of request which has fallbacked
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* @stat_bytes: total data size done by this template
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*/
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struct sl3516_ce_alg_template {
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u32 type;
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u32 mode;
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struct sl3516_ce_dev *ce;
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union {
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struct skcipher_alg skcipher;
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} alg;
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unsigned long stat_req;
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unsigned long stat_fb;
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unsigned long stat_bytes;
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};
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int sl3516_ce_enqueue(struct crypto_async_request *areq, u32 type);
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int sl3516_ce_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
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unsigned int keylen);
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int sl3516_ce_cipher_init(struct crypto_tfm *tfm);
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void sl3516_ce_cipher_exit(struct crypto_tfm *tfm);
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int sl3516_ce_skdecrypt(struct skcipher_request *areq);
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int sl3516_ce_skencrypt(struct skcipher_request *areq);
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int sl3516_ce_run_task(struct sl3516_ce_dev *ce,
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struct sl3516_ce_cipher_req_ctx *rctx, const char *name);
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int sl3516_ce_rng_register(struct sl3516_ce_dev *ce);
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void sl3516_ce_rng_unregister(struct sl3516_ce_dev *ce);
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