376 lines
11 KiB
C
376 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only
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* Copyright (C) 2020 Marvell.
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*/
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#ifndef __OTX2_CPTLF_H
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#define __OTX2_CPTLF_H
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#include <linux/soc/marvell/octeontx2/asm.h>
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#include <mbox.h>
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#include <rvu.h>
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#include "otx2_cpt_common.h"
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#include "otx2_cpt_reqmgr.h"
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/*
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* CPT instruction and pending queues user requested length in CPT_INST_S msgs
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*/
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#define OTX2_CPT_USER_REQUESTED_QLEN_MSGS 8200
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/*
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* CPT instruction queue size passed to HW is in units of 40*CPT_INST_S
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* messages.
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*/
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#define OTX2_CPT_SIZE_DIV40 (OTX2_CPT_USER_REQUESTED_QLEN_MSGS/40)
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/*
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* CPT instruction and pending queues length in CPT_INST_S messages
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*/
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#define OTX2_CPT_INST_QLEN_MSGS ((OTX2_CPT_SIZE_DIV40 - 1) * 40)
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/*
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* LDWB is getting incorrectly used when IQB_LDWB = 1 and CPT instruction
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* queue has less than 320 free entries. So, increase HW instruction queue
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* size by 320 and give 320 entries less for SW/NIX RX as a workaround.
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*/
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#define OTX2_CPT_INST_QLEN_EXTRA_BYTES (320 * OTX2_CPT_INST_SIZE)
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#define OTX2_CPT_EXTRA_SIZE_DIV40 (320/40)
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/* CPT instruction queue length in bytes */
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#define OTX2_CPT_INST_QLEN_BYTES \
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((OTX2_CPT_SIZE_DIV40 * 40 * OTX2_CPT_INST_SIZE) + \
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OTX2_CPT_INST_QLEN_EXTRA_BYTES)
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/* CPT instruction group queue length in bytes */
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#define OTX2_CPT_INST_GRP_QLEN_BYTES \
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((OTX2_CPT_SIZE_DIV40 + OTX2_CPT_EXTRA_SIZE_DIV40) * 16)
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/* CPT FC length in bytes */
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#define OTX2_CPT_Q_FC_LEN 128
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/* CPT instruction queue alignment */
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#define OTX2_CPT_INST_Q_ALIGNMENT 128
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/* Mask which selects all engine groups */
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#define OTX2_CPT_ALL_ENG_GRPS_MASK 0xFF
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/* Maximum LFs supported in OcteonTX2 for CPT */
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#define OTX2_CPT_MAX_LFS_NUM 64
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/* Queue priority */
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#define OTX2_CPT_QUEUE_HI_PRIO 0x1
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#define OTX2_CPT_QUEUE_LOW_PRIO 0x0
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enum otx2_cptlf_state {
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OTX2_CPTLF_IN_RESET,
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OTX2_CPTLF_STARTED,
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};
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struct otx2_cpt_inst_queue {
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u8 *vaddr;
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u8 *real_vaddr;
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dma_addr_t dma_addr;
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dma_addr_t real_dma_addr;
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u32 size;
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};
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struct otx2_cptlfs_info;
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struct otx2_cptlf_wqe {
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struct tasklet_struct work;
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struct otx2_cptlfs_info *lfs;
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u8 lf_num;
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};
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struct otx2_cptlf_info {
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struct otx2_cptlfs_info *lfs; /* Ptr to cptlfs_info struct */
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void __iomem *lmtline; /* Address of LMTLINE */
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void __iomem *ioreg; /* LMTLINE send register */
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int msix_offset; /* MSI-X interrupts offset */
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cpumask_var_t affinity_mask; /* IRQs affinity mask */
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u8 irq_name[OTX2_CPT_LF_MSIX_VECTORS][32];/* Interrupts name */
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u8 is_irq_reg[OTX2_CPT_LF_MSIX_VECTORS]; /* Is interrupt registered */
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u8 slot; /* Slot number of this LF */
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struct otx2_cpt_inst_queue iqueue;/* Instruction queue */
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struct otx2_cpt_pending_queue pqueue; /* Pending queue */
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struct otx2_cptlf_wqe *wqe; /* Tasklet work info */
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};
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struct cpt_hw_ops {
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void (*send_cmd)(union otx2_cpt_inst_s *cptinst, u32 insts_num,
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struct otx2_cptlf_info *lf);
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u8 (*cpt_get_compcode)(union otx2_cpt_res_s *result);
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u8 (*cpt_get_uc_compcode)(union otx2_cpt_res_s *result);
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};
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struct otx2_cptlfs_info {
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/* Registers start address of VF/PF LFs are attached to */
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void __iomem *reg_base;
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#define LMTLINE_SIZE 128
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void __iomem *lmt_base;
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struct pci_dev *pdev; /* Device LFs are attached to */
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struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM];
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struct otx2_mbox *mbox;
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struct cpt_hw_ops *ops;
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u8 are_lfs_attached; /* Whether CPT LFs are attached */
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u8 lfs_num; /* Number of CPT LFs */
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u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */
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u8 kvf_limits; /* Kernel crypto limits */
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atomic_t state; /* LF's state. started/reset */
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int blkaddr; /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */
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};
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static inline void otx2_cpt_free_instruction_queues(
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struct otx2_cptlfs_info *lfs)
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{
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struct otx2_cpt_inst_queue *iq;
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int i;
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for (i = 0; i < lfs->lfs_num; i++) {
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iq = &lfs->lf[i].iqueue;
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if (iq->real_vaddr)
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dma_free_coherent(&lfs->pdev->dev,
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iq->size,
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iq->real_vaddr,
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iq->real_dma_addr);
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iq->real_vaddr = NULL;
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iq->vaddr = NULL;
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}
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}
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static inline int otx2_cpt_alloc_instruction_queues(
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struct otx2_cptlfs_info *lfs)
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{
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struct otx2_cpt_inst_queue *iq;
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int ret = 0, i;
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if (!lfs->lfs_num)
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return -EINVAL;
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for (i = 0; i < lfs->lfs_num; i++) {
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iq = &lfs->lf[i].iqueue;
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iq->size = OTX2_CPT_INST_QLEN_BYTES +
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OTX2_CPT_Q_FC_LEN +
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OTX2_CPT_INST_GRP_QLEN_BYTES +
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OTX2_CPT_INST_Q_ALIGNMENT;
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iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size,
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&iq->real_dma_addr, GFP_KERNEL);
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if (!iq->real_vaddr) {
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ret = -ENOMEM;
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goto error;
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}
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iq->vaddr = iq->real_vaddr + OTX2_CPT_INST_GRP_QLEN_BYTES;
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iq->dma_addr = iq->real_dma_addr + OTX2_CPT_INST_GRP_QLEN_BYTES;
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/* Align pointers */
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iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_CPT_INST_Q_ALIGNMENT);
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iq->dma_addr = PTR_ALIGN(iq->dma_addr,
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OTX2_CPT_INST_Q_ALIGNMENT);
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}
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return 0;
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error:
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otx2_cpt_free_instruction_queues(lfs);
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return ret;
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}
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static inline void otx2_cptlf_set_iqueues_base_addr(
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struct otx2_cptlfs_info *lfs)
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{
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union otx2_cptx_lf_q_base lf_q_base;
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int slot;
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for (slot = 0; slot < lfs->lfs_num; slot++) {
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lf_q_base.u = lfs->lf[slot].iqueue.dma_addr;
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otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
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OTX2_CPT_LF_Q_BASE, lf_q_base.u);
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}
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}
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static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf)
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{
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union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 };
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lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40 +
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OTX2_CPT_EXTRA_SIZE_DIV40;
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_Q_SIZE, lf_q_size.u);
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}
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static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs)
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{
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int slot;
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for (slot = 0; slot < lfs->lfs_num; slot++)
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otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]);
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}
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static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf)
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{
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union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 };
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union otx2_cptx_lf_inprog lf_inprog;
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int timeout = 20;
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/* Disable instructions enqueuing */
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_CTL, lf_ctl.u);
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/* Wait for instruction queue to become empty */
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do {
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lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0,
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lf->slot, OTX2_CPT_LF_INPROG);
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if (!lf_inprog.s.inflight)
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break;
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usleep_range(10000, 20000);
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if (timeout-- < 0) {
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dev_err(&lf->lfs->pdev->dev,
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"Error LF %d is still busy.\n", lf->slot);
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break;
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}
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} while (1);
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/*
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* Disable executions in the LF's queue,
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* the queue should be empty at this point
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*/
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lf_inprog.s.eena = 0x0;
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_INPROG, lf_inprog.u);
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}
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static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs)
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{
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int slot;
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for (slot = 0; slot < lfs->lfs_num; slot++)
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otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]);
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}
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static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf,
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bool enable)
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{
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union otx2_cptx_lf_ctl lf_ctl;
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lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_CTL);
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/* Set iqueue's enqueuing */
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lf_ctl.s.ena = enable ? 0x1 : 0x0;
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_CTL, lf_ctl.u);
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}
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static inline void otx2_cptlf_enable_iqueue_enq(struct otx2_cptlf_info *lf)
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{
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otx2_cptlf_set_iqueue_enq(lf, true);
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}
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static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf,
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bool enable)
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{
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union otx2_cptx_lf_inprog lf_inprog;
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lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_INPROG);
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/* Set iqueue's execution */
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lf_inprog.s.eena = enable ? 0x1 : 0x0;
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_INPROG, lf_inprog.u);
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}
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static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf)
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{
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otx2_cptlf_set_iqueue_exec(lf, true);
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}
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static inline void otx2_cptlf_disable_iqueue_exec(struct otx2_cptlf_info *lf)
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{
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otx2_cptlf_set_iqueue_exec(lf, false);
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}
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static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs)
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{
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int slot;
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for (slot = 0; slot < lfs->lfs_num; slot++) {
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otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]);
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otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]);
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}
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}
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static inline void otx2_cpt_fill_inst(union otx2_cpt_inst_s *cptinst,
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struct otx2_cpt_iq_command *iq_cmd,
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u64 comp_baddr)
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{
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cptinst->u[0] = 0x0;
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cptinst->s.doneint = true;
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cptinst->s.res_addr = comp_baddr;
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cptinst->u[2] = 0x0;
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cptinst->u[3] = 0x0;
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cptinst->s.ei0 = iq_cmd->cmd.u;
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cptinst->s.ei1 = iq_cmd->dptr;
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cptinst->s.ei2 = iq_cmd->rptr;
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cptinst->s.ei3 = iq_cmd->cptr.u;
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}
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|
|
/*
|
|||
|
|
* On OcteonTX2 platform the parameter insts_num is used as a count of
|
|||
|
|
* instructions to be enqueued. The valid values for insts_num are:
|
|||
|
|
* 1 - 1 CPT instruction will be enqueued during LMTST operation
|
|||
|
|
* 2 - 2 CPT instructions will be enqueued during LMTST operation
|
|||
|
|
*/
|
|||
|
|
static inline void otx2_cpt_send_cmd(union otx2_cpt_inst_s *cptinst,
|
|||
|
|
u32 insts_num, struct otx2_cptlf_info *lf)
|
|||
|
|
{
|
|||
|
|
void __iomem *lmtline = lf->lmtline;
|
|||
|
|
long ret;
|
|||
|
|
|
|||
|
|
/*
|
|||
|
|
* Make sure memory areas pointed in CPT_INST_S
|
|||
|
|
* are flushed before the instruction is sent to CPT
|
|||
|
|
*/
|
|||
|
|
dma_wmb();
|
|||
|
|
|
|||
|
|
do {
|
|||
|
|
/* Copy CPT command to LMTLINE */
|
|||
|
|
memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);
|
|||
|
|
|
|||
|
|
/*
|
|||
|
|
* LDEOR initiates atomic transfer to I/O device
|
|||
|
|
* The following will cause the LMTST to fail (the LDEOR
|
|||
|
|
* returns zero):
|
|||
|
|
* - No stores have been performed to the LMTLINE since it was
|
|||
|
|
* last invalidated.
|
|||
|
|
* - The bytes which have been stored to LMTLINE since it was
|
|||
|
|
* last invalidated form a pattern that is non-contiguous, does
|
|||
|
|
* not start at byte 0, or does not end on a 8-byte boundary.
|
|||
|
|
* (i.e.comprises a formation of other than 1–16 8-byte
|
|||
|
|
* words.)
|
|||
|
|
*
|
|||
|
|
* These rules are designed such that an operating system
|
|||
|
|
* context switch or hypervisor guest switch need have no
|
|||
|
|
* knowledge of the LMTST operations; the switch code does not
|
|||
|
|
* need to store to LMTCANCEL. Also note as LMTLINE data cannot
|
|||
|
|
* be read, there is no information leakage between processes.
|
|||
|
|
*/
|
|||
|
|
ret = otx2_lmt_flush(lf->ioreg);
|
|||
|
|
|
|||
|
|
} while (!ret);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs)
|
|||
|
|
{
|
|||
|
|
return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,
|
|||
|
|
int lfs_num);
|
|||
|
|
void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);
|
|||
|
|
int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs);
|
|||
|
|
void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs);
|
|||
|
|
void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs);
|
|||
|
|
int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs);
|
|||
|
|
|
|||
|
|
#endif /* __OTX2_CPTLF_H */
|