269 lines
8.4 KiB
C
269 lines
8.4 KiB
C
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// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2020 Intel Corporation */
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#include "adf_common_drv.h"
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#include "adf_gen2_hw_data.h"
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#include "icp_qat_hw.h"
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#include <linux/pci.h>
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u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self)
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{
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if (!self || !self->accel_mask)
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return 0;
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return hweight16(self->accel_mask);
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}
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EXPORT_SYMBOL_GPL(adf_gen2_get_num_accels);
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u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self)
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{
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if (!self || !self->ae_mask)
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return 0;
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return hweight32(self->ae_mask);
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}
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EXPORT_SYMBOL_GPL(adf_gen2_get_num_aes);
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void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);
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unsigned long accel_mask = hw_data->accel_mask;
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unsigned long ae_mask = hw_data->ae_mask;
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unsigned int val, i;
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/* Enable Accel Engine error detection & correction */
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for_each_set_bit(i, &ae_mask, hw_data->num_engines) {
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val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i));
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val |= ADF_GEN2_ENABLE_AE_ECC_ERR;
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i), val);
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val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_AE_MISC_CONTROL(i));
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val |= ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR;
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_MISC_CONTROL(i), val);
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}
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/* Enable shared memory error detection & correction */
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for_each_set_bit(i, &accel_mask, hw_data->num_accel) {
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val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_UERRSSMSH(i));
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val |= ADF_GEN2_ERRSSMSH_EN;
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_UERRSSMSH(i), val);
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val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_CERRSSMSH(i));
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val |= ADF_GEN2_ERRSSMSH_EN;
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_CERRSSMSH(i), val);
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}
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}
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EXPORT_SYMBOL_GPL(adf_gen2_enable_error_correction);
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void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
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int num_a_regs, int num_b_regs)
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{
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void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);
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u32 reg;
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int i;
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/* Set/Unset Valid bit in AE Thread to PCIe Function Mapping Group A */
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for (i = 0; i < num_a_regs; i++) {
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reg = READ_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i);
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if (enable)
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reg |= AE2FUNCTION_MAP_VALID;
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else
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reg &= ~AE2FUNCTION_MAP_VALID;
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WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i, reg);
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}
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/* Set/Unset Valid bit in AE Thread to PCIe Function Mapping Group B */
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for (i = 0; i < num_b_regs; i++) {
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reg = READ_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i);
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if (enable)
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reg |= AE2FUNCTION_MAP_VALID;
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else
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reg &= ~AE2FUNCTION_MAP_VALID;
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WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i, reg);
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}
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}
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EXPORT_SYMBOL_GPL(adf_gen2_cfg_iov_thds);
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void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info)
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{
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admin_csrs_info->mailbox_offset = ADF_MAILBOX_BASE_OFFSET;
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admin_csrs_info->admin_msg_ur = ADF_ADMINMSGUR_OFFSET;
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admin_csrs_info->admin_msg_lr = ADF_ADMINMSGLR_OFFSET;
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}
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EXPORT_SYMBOL_GPL(adf_gen2_get_admin_info);
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void adf_gen2_get_arb_info(struct arb_info *arb_info)
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{
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arb_info->arb_cfg = ADF_ARB_CONFIG;
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arb_info->arb_offset = ADF_ARB_OFFSET;
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arb_info->wt2sam_offset = ADF_ARB_WRK_2_SER_MAP_OFFSET;
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}
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EXPORT_SYMBOL_GPL(adf_gen2_get_arb_info);
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void adf_gen2_enable_ints(struct adf_accel_dev *accel_dev)
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{
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void __iomem *addr = adf_get_pmisc_base(accel_dev);
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u32 val;
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val = accel_dev->pf.vf_info ? 0 : BIT_ULL(GET_MAX_BANKS(accel_dev)) - 1;
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/* Enable bundle and misc interrupts */
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ADF_CSR_WR(addr, ADF_GEN2_SMIAPF0_MASK_OFFSET, val);
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ADF_CSR_WR(addr, ADF_GEN2_SMIAPF1_MASK_OFFSET, ADF_GEN2_SMIA1_MASK);
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}
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EXPORT_SYMBOL_GPL(adf_gen2_enable_ints);
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static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
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{
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return BUILD_RING_BASE_ADDR(addr, size);
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}
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static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
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{
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return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
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}
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static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
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u32 value)
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{
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WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
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}
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static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
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{
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return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
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}
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static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
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u32 value)
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{
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WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
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}
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static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
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{
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return READ_CSR_E_STAT(csr_base_addr, bank);
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}
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static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
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u32 ring, u32 value)
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{
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WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
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}
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static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
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dma_addr_t addr)
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{
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WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
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}
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static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value)
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{
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WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
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}
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static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
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{
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WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
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}
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static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank,
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u32 value)
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{
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WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
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}
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static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
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u32 value)
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{
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WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
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}
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static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
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u32 value)
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{
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WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
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}
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static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
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u32 value)
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{
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WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
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}
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void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
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{
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csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
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csr_ops->read_csr_ring_head = read_csr_ring_head;
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csr_ops->write_csr_ring_head = write_csr_ring_head;
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csr_ops->read_csr_ring_tail = read_csr_ring_tail;
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csr_ops->write_csr_ring_tail = write_csr_ring_tail;
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csr_ops->read_csr_e_stat = read_csr_e_stat;
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csr_ops->write_csr_ring_config = write_csr_ring_config;
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csr_ops->write_csr_ring_base = write_csr_ring_base;
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csr_ops->write_csr_int_flag = write_csr_int_flag;
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csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
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csr_ops->write_csr_int_col_en = write_csr_int_col_en;
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csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
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csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
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csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
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}
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EXPORT_SYMBOL_GPL(adf_gen2_init_hw_csr_ops);
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u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
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u32 straps = hw_data->straps;
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u32 fuses = hw_data->fuses;
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u32 legfuses;
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u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
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ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
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ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
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ICP_ACCEL_CAPABILITIES_CIPHER |
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ICP_ACCEL_CAPABILITIES_COMPRESSION;
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/* Read accelerator capabilities mask */
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pci_read_config_dword(pdev, ADF_DEVICE_LEGFUSE_OFFSET, &legfuses);
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/* A set bit in legfuses means the feature is OFF in this SKU */
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if (legfuses & ICP_ACCEL_MASK_CIPHER_SLICE) {
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
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}
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if (legfuses & ICP_ACCEL_MASK_PKE_SLICE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
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if (legfuses & ICP_ACCEL_MASK_AUTH_SLICE) {
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capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
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}
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if (legfuses & ICP_ACCEL_MASK_COMPRESS_SLICE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
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if ((straps | fuses) & ADF_POWERGATE_PKE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
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if ((straps | fuses) & ADF_POWERGATE_DC)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
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return capabilities;
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}
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EXPORT_SYMBOL_GPL(adf_gen2_get_accel_cap);
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void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);
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u32 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;
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u32 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;
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unsigned long accel_mask = hw_data->accel_mask;
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u32 i = 0;
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/* Configures WDT timers */
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for_each_set_bit(i, &accel_mask, hw_data->num_accel) {
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/* Enable WDT for sym and dc */
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ADF_CSR_WR(pmisc_addr, ADF_SSMWDT(i), timer_val);
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/* Enable WDT for pke */
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ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKE(i), timer_val_pke);
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}
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}
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EXPORT_SYMBOL_GPL(adf_gen2_set_ssm_wdtimer);
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