84 lines
3.5 KiB
C
84 lines
3.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2022 Intel Corporation */
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#include "adf_accel_devices.h"
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#include "icp_qat_fw_comp.h"
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#include "icp_qat_hw_20_comp.h"
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#include "adf_gen4_dc.h"
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static void qat_comp_build_deflate(void *ctx)
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{
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struct icp_qat_fw_comp_req *req_tmpl =
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(struct icp_qat_fw_comp_req *)ctx;
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struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
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struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
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struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
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struct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr = {0};
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struct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr = {0};
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struct icp_qat_hw_decomp_20_config_csr_lower hw_decomp_lower_csr = {0};
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u32 upper_val;
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u32 lower_val;
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memset(req_tmpl, 0, sizeof(*req_tmpl));
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header->hdr_flags =
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ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
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header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
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header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
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header->comn_req_flags =
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ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
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QAT_COMN_PTR_TYPE_SGL);
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header->serv_specif_flags =
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ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
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ICP_QAT_FW_COMP_AUTO_SELECT_BEST,
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ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
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ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
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ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
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hw_comp_lower_csr.skip_ctrl = ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL;
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hw_comp_lower_csr.algo = ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77;
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hw_comp_lower_csr.lllbd = ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED;
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hw_comp_lower_csr.sd = ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1;
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hw_comp_lower_csr.hash_update = ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW;
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hw_comp_lower_csr.edmm = ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED;
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hw_comp_upper_csr.nice = ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL;
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hw_comp_upper_csr.lazy = ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL;
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upper_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(hw_comp_upper_csr);
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lower_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(hw_comp_lower_csr);
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cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
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cd_pars->u.sl.comp_slice_cfg_word[1] = upper_val;
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req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
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req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
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req_pars->req_par_flags =
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ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
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ICP_QAT_FW_COMP_EOP,
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ICP_QAT_FW_COMP_BFINAL,
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ICP_QAT_FW_COMP_CNV,
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ICP_QAT_FW_COMP_CNV_RECOVERY,
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ICP_QAT_FW_COMP_NO_CNV_DFX,
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ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
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ICP_QAT_FW_COMP_NO_XXHASH_ACC,
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ICP_QAT_FW_COMP_CNV_ERROR_NONE,
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ICP_QAT_FW_COMP_NO_APPEND_CRC,
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ICP_QAT_FW_COMP_NO_DROP_DATA);
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/* Fill second half of the template for decompression */
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memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
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req_tmpl++;
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header = &req_tmpl->comn_hdr;
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header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
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cd_pars = &req_tmpl->cd_pars;
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hw_decomp_lower_csr.algo = ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE;
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lower_val = ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(hw_decomp_lower_csr);
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cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
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cd_pars->u.sl.comp_slice_cfg_word[1] = 0;
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}
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void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops)
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{
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dc_ops->build_deflate_ctx = qat_comp_build_deflate;
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}
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EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops);
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