191 lines
6.0 KiB
C
191 lines
6.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* 2006-2009 (C) DENX Software Engineering.
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*
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* Author: Yuri Tikhonov <yur@emcraft.com>
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*/
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#ifndef _PPC440SPE_ADMA_H
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#define _PPC440SPE_ADMA_H
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#include <linux/types.h>
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#include "dma.h"
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#include "xor.h"
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#define to_ppc440spe_adma_chan(chan) \
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container_of(chan, struct ppc440spe_adma_chan, common)
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#define to_ppc440spe_adma_device(dev) \
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container_of(dev, struct ppc440spe_adma_device, common)
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#define tx_to_ppc440spe_adma_slot(tx) \
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container_of(tx, struct ppc440spe_adma_desc_slot, async_tx)
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/* Default polynomial (for 440SP is only available) */
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#define PPC440SPE_DEFAULT_POLY 0x4d
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#define PPC440SPE_ADMA_ENGINES_NUM (XOR_ENGINES_NUM + DMA_ENGINES_NUM)
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#define PPC440SPE_ADMA_WATCHDOG_MSEC 3
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#define PPC440SPE_ADMA_THRESHOLD 1
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#define PPC440SPE_DMA0_ID 0
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#define PPC440SPE_DMA1_ID 1
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#define PPC440SPE_XOR_ID 2
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#define PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT 0xFFFFFFUL
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/* this is the XOR_CBBCR width */
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#define PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT (1 << 31)
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#define PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT
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#define PPC440SPE_RXOR_RUN 0
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#define MQ0_CF2H_RXOR_BS_MASK 0x1FF
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#undef ADMA_LL_DEBUG
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/**
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* struct ppc440spe_adma_device - internal representation of an ADMA device
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* @dev: device
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* @dma_reg: base for DMAx register access
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* @xor_reg: base for XOR register access
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* @i2o_reg: base for I2O register access
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* @id: HW ADMA Device selector
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* @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
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* @dma_desc_pool: base of DMA descriptor region (DMA address)
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* @pool_size: size of the pool
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* @irq: DMAx or XOR irq number
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* @err_irq: DMAx error irq number
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* @common: embedded struct dma_device
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*/
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struct ppc440spe_adma_device {
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struct device *dev;
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struct dma_regs __iomem *dma_reg;
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struct xor_regs __iomem *xor_reg;
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struct i2o_regs __iomem *i2o_reg;
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int id;
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void *dma_desc_pool_virt;
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dma_addr_t dma_desc_pool;
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size_t pool_size;
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int irq;
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int err_irq;
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struct dma_device common;
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};
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/**
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* struct ppc440spe_adma_chan - internal representation of an ADMA channel
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* @lock: serializes enqueue/dequeue operations to the slot pool
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* @device: parent device
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* @chain: device chain view of the descriptors
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* @common: common dmaengine channel object members
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* @all_slots: complete domain of slots usable by the channel
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* @pending: allows batching of hardware operations
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* @slots_allocated: records the actual size of the descriptor slot pool
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* @hw_chain_inited: h/w descriptor chain initialization flag
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* @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
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* @needs_unmap: if buffers should not be unmapped upon final processing
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* @pdest_page: P destination page for async validate operation
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* @qdest_page: Q destination page for async validate operation
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* @pdest: P dma addr for async validate operation
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* @qdest: Q dma addr for async validate operation
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*/
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struct ppc440spe_adma_chan {
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spinlock_t lock;
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struct ppc440spe_adma_device *device;
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struct list_head chain;
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struct dma_chan common;
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struct list_head all_slots;
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struct ppc440spe_adma_desc_slot *last_used;
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int pending;
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int slots_allocated;
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int hw_chain_inited;
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struct tasklet_struct irq_tasklet;
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u8 needs_unmap;
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struct page *pdest_page;
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struct page *qdest_page;
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dma_addr_t pdest;
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dma_addr_t qdest;
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};
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struct ppc440spe_rxor {
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u32 addrl;
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u32 addrh;
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int len;
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int xor_count;
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int addr_count;
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int desc_count;
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int state;
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};
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/**
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* struct ppc440spe_adma_desc_slot - PPC440SPE-ADMA software descriptor
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* @phys: hardware address of the hardware descriptor chain
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* @group_head: first operation in a transaction
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* @hw_next: pointer to the next descriptor in chain
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* @async_tx: support for the async_tx api
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* @slot_node: node on the iop_adma_chan.all_slots list
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* @chain_node: node on the op_adma_chan.chain list
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* @group_list: list of slots that make up a multi-descriptor transaction
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* for example transfer lengths larger than the supported hw max
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* @unmap_len: transaction bytecount
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* @hw_desc: virtual address of the hardware descriptor chain
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* @stride: currently chained or not
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* @idx: pool index
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* @slot_cnt: total slots used in an transaction (group of operations)
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* @src_cnt: number of sources set in this descriptor
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* @dst_cnt: number of destinations set in the descriptor
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* @slots_per_op: number of slots per operation
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* @descs_per_op: number of slot per P/Q operation see comment
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* for ppc440spe_prep_dma_pqxor function
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* @flags: desc state/type
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* @reverse_flags: 1 if a corresponding rxor address uses reversed address order
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* @xor_check_result: result of zero sum
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* @crc32_result: result crc calculation
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*/
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struct ppc440spe_adma_desc_slot {
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dma_addr_t phys;
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struct ppc440spe_adma_desc_slot *group_head;
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struct ppc440spe_adma_desc_slot *hw_next;
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struct dma_async_tx_descriptor async_tx;
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struct list_head slot_node;
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struct list_head chain_node; /* node in channel ops list */
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struct list_head group_list; /* list */
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unsigned int unmap_len;
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void *hw_desc;
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u16 stride;
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u16 idx;
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u16 slot_cnt;
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u8 src_cnt;
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u8 dst_cnt;
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u8 slots_per_op;
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u8 descs_per_op;
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unsigned long flags;
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unsigned long reverse_flags[8];
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#define PPC440SPE_DESC_INT 0 /* generate interrupt on complete */
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#define PPC440SPE_ZERO_P 1 /* clear P destionaion */
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#define PPC440SPE_ZERO_Q 2 /* clear Q destination */
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#define PPC440SPE_COHERENT 3 /* src/dst are coherent */
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#define PPC440SPE_DESC_WXOR 4 /* WXORs are in chain */
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#define PPC440SPE_DESC_RXOR 5 /* RXOR is in chain */
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#define PPC440SPE_DESC_RXOR123 8 /* CDB for RXOR123 operation */
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#define PPC440SPE_DESC_RXOR124 9 /* CDB for RXOR124 operation */
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#define PPC440SPE_DESC_RXOR125 10 /* CDB for RXOR125 operation */
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#define PPC440SPE_DESC_RXOR12 11 /* CDB for RXOR12 operation */
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#define PPC440SPE_DESC_RXOR_REV 12 /* CDB has srcs in reversed order */
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#define PPC440SPE_DESC_PCHECK 13
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#define PPC440SPE_DESC_QCHECK 14
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#define PPC440SPE_DESC_RXOR_MSK 0x3
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struct ppc440spe_rxor rxor_cursor;
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union {
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u32 *xor_check_result;
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u32 *crc32_result;
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};
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};
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#endif /* _PPC440SPE_ADMA_H */
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