378 lines
9.0 KiB
C
378 lines
9.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
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*/
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#include <linux/kernel.h>
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#include "k3-psil-priv.h"
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#define PSIL_PDMA_XY_TR(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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}, \
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}
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#define PSIL_PDMA_XY_PKT(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pkt_mode = 1, \
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}, \
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}
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#define PSIL_PDMA_MCASP(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pdma_acc32 = 1, \
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.pdma_burst = 1, \
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}, \
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}
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#define PSIL_ETHERNET(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 16, \
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}, \
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}
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#define PSIL_SA2UL(x, tx) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 64, \
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.notdpkt = tx, \
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}, \
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}
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#define PSIL_CSI2RX(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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}, \
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}
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/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
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static struct psil_ep j721e_src_ep_map[] = {
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/* SA2UL */
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PSIL_SA2UL(0x4000, 0),
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PSIL_SA2UL(0x4001, 0),
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PSIL_SA2UL(0x4002, 0),
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PSIL_SA2UL(0x4003, 0),
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/* PRU_ICSSG0 */
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PSIL_ETHERNET(0x4100),
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PSIL_ETHERNET(0x4101),
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PSIL_ETHERNET(0x4102),
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PSIL_ETHERNET(0x4103),
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/* PRU_ICSSG1 */
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PSIL_ETHERNET(0x4200),
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PSIL_ETHERNET(0x4201),
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PSIL_ETHERNET(0x4202),
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PSIL_ETHERNET(0x4203),
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/* PDMA6 (PSIL_PDMA_MCASP_G0) - McASP0-2 */
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PSIL_PDMA_MCASP(0x4400),
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PSIL_PDMA_MCASP(0x4401),
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PSIL_PDMA_MCASP(0x4402),
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/* PDMA7 (PSIL_PDMA_MCASP_G1) - McASP3-11 */
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PSIL_PDMA_MCASP(0x4500),
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PSIL_PDMA_MCASP(0x4501),
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PSIL_PDMA_MCASP(0x4502),
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PSIL_PDMA_MCASP(0x4503),
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PSIL_PDMA_MCASP(0x4504),
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PSIL_PDMA_MCASP(0x4505),
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PSIL_PDMA_MCASP(0x4506),
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PSIL_PDMA_MCASP(0x4507),
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PSIL_PDMA_MCASP(0x4508),
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/* PDMA8 (PDMA_MISC_G0) - SPI0-1 */
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PSIL_PDMA_XY_PKT(0x4600),
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PSIL_PDMA_XY_PKT(0x4601),
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PSIL_PDMA_XY_PKT(0x4602),
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PSIL_PDMA_XY_PKT(0x4603),
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PSIL_PDMA_XY_PKT(0x4604),
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PSIL_PDMA_XY_PKT(0x4605),
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PSIL_PDMA_XY_PKT(0x4606),
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PSIL_PDMA_XY_PKT(0x4607),
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/* PDMA9 (PDMA_MISC_G1) - SPI2-3 */
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PSIL_PDMA_XY_PKT(0x460c),
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PSIL_PDMA_XY_PKT(0x460d),
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PSIL_PDMA_XY_PKT(0x460e),
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PSIL_PDMA_XY_PKT(0x460f),
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PSIL_PDMA_XY_PKT(0x4610),
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PSIL_PDMA_XY_PKT(0x4611),
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PSIL_PDMA_XY_PKT(0x4612),
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PSIL_PDMA_XY_PKT(0x4613),
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/* PDMA10 (PDMA_MISC_G2) - SPI4-5 */
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PSIL_PDMA_XY_PKT(0x4618),
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PSIL_PDMA_XY_PKT(0x4619),
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PSIL_PDMA_XY_PKT(0x461a),
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PSIL_PDMA_XY_PKT(0x461b),
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PSIL_PDMA_XY_PKT(0x461c),
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PSIL_PDMA_XY_PKT(0x461d),
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PSIL_PDMA_XY_PKT(0x461e),
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PSIL_PDMA_XY_PKT(0x461f),
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/* PDMA11 (PDMA_MISC_G3) */
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PSIL_PDMA_XY_PKT(0x4624),
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PSIL_PDMA_XY_PKT(0x4625),
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PSIL_PDMA_XY_PKT(0x4626),
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PSIL_PDMA_XY_PKT(0x4627),
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PSIL_PDMA_XY_PKT(0x4628),
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PSIL_PDMA_XY_PKT(0x4629),
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PSIL_PDMA_XY_PKT(0x4630),
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PSIL_PDMA_XY_PKT(0x463a),
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/* PDMA13 (PDMA_USART_G0) - UART0-1 */
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PSIL_PDMA_XY_PKT(0x4700),
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PSIL_PDMA_XY_PKT(0x4701),
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/* PDMA14 (PDMA_USART_G1) - UART2-3 */
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PSIL_PDMA_XY_PKT(0x4702),
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PSIL_PDMA_XY_PKT(0x4703),
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/* PDMA15 (PDMA_USART_G2) - UART4-9 */
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PSIL_PDMA_XY_PKT(0x4704),
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PSIL_PDMA_XY_PKT(0x4705),
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PSIL_PDMA_XY_PKT(0x4706),
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PSIL_PDMA_XY_PKT(0x4707),
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PSIL_PDMA_XY_PKT(0x4708),
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PSIL_PDMA_XY_PKT(0x4709),
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/* CSI2RX */
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PSIL_CSI2RX(0x4940),
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PSIL_CSI2RX(0x4941),
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PSIL_CSI2RX(0x4942),
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PSIL_CSI2RX(0x4943),
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PSIL_CSI2RX(0x4944),
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PSIL_CSI2RX(0x4945),
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PSIL_CSI2RX(0x4946),
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PSIL_CSI2RX(0x4947),
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PSIL_CSI2RX(0x4948),
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PSIL_CSI2RX(0x4949),
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PSIL_CSI2RX(0x494a),
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PSIL_CSI2RX(0x494b),
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PSIL_CSI2RX(0x494c),
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PSIL_CSI2RX(0x494d),
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PSIL_CSI2RX(0x494e),
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PSIL_CSI2RX(0x494f),
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PSIL_CSI2RX(0x4950),
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PSIL_CSI2RX(0x4951),
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PSIL_CSI2RX(0x4952),
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PSIL_CSI2RX(0x4953),
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PSIL_CSI2RX(0x4954),
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PSIL_CSI2RX(0x4955),
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PSIL_CSI2RX(0x4956),
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PSIL_CSI2RX(0x4957),
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PSIL_CSI2RX(0x4958),
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PSIL_CSI2RX(0x4959),
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PSIL_CSI2RX(0x495a),
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PSIL_CSI2RX(0x495b),
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PSIL_CSI2RX(0x495c),
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PSIL_CSI2RX(0x495d),
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PSIL_CSI2RX(0x495e),
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PSIL_CSI2RX(0x495f),
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PSIL_CSI2RX(0x4960),
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PSIL_CSI2RX(0x4961),
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PSIL_CSI2RX(0x4962),
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PSIL_CSI2RX(0x4963),
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PSIL_CSI2RX(0x4964),
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PSIL_CSI2RX(0x4965),
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PSIL_CSI2RX(0x4966),
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PSIL_CSI2RX(0x4967),
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PSIL_CSI2RX(0x4968),
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PSIL_CSI2RX(0x4969),
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PSIL_CSI2RX(0x496a),
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PSIL_CSI2RX(0x496b),
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PSIL_CSI2RX(0x496c),
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PSIL_CSI2RX(0x496d),
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PSIL_CSI2RX(0x496e),
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PSIL_CSI2RX(0x496f),
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PSIL_CSI2RX(0x4970),
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PSIL_CSI2RX(0x4971),
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PSIL_CSI2RX(0x4972),
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PSIL_CSI2RX(0x4973),
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PSIL_CSI2RX(0x4974),
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PSIL_CSI2RX(0x4975),
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PSIL_CSI2RX(0x4976),
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PSIL_CSI2RX(0x4977),
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PSIL_CSI2RX(0x4978),
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PSIL_CSI2RX(0x4979),
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PSIL_CSI2RX(0x497a),
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PSIL_CSI2RX(0x497b),
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PSIL_CSI2RX(0x497c),
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PSIL_CSI2RX(0x497d),
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PSIL_CSI2RX(0x497e),
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PSIL_CSI2RX(0x497f),
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/* CPSW9 */
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PSIL_ETHERNET(0x4a00),
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/* CPSW0 */
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PSIL_ETHERNET(0x7000),
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/* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
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PSIL_PDMA_XY_PKT(0x7100),
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PSIL_PDMA_XY_PKT(0x7101),
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PSIL_PDMA_XY_PKT(0x7102),
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PSIL_PDMA_XY_PKT(0x7103),
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/* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
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PSIL_PDMA_XY_PKT(0x7200),
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PSIL_PDMA_XY_PKT(0x7201),
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PSIL_PDMA_XY_PKT(0x7202),
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PSIL_PDMA_XY_PKT(0x7203),
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PSIL_PDMA_XY_PKT(0x7204),
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PSIL_PDMA_XY_PKT(0x7205),
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PSIL_PDMA_XY_PKT(0x7206),
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PSIL_PDMA_XY_PKT(0x7207),
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/* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
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PSIL_PDMA_XY_PKT(0x7300),
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/* MCU_PDMA_ADC - ADC0-1 */
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PSIL_PDMA_XY_TR(0x7400),
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PSIL_PDMA_XY_TR(0x7401),
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PSIL_PDMA_XY_TR(0x7402),
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PSIL_PDMA_XY_TR(0x7403),
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/* SA2UL */
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PSIL_SA2UL(0x7500, 0),
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PSIL_SA2UL(0x7501, 0),
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PSIL_SA2UL(0x7502, 0),
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PSIL_SA2UL(0x7503, 0),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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static struct psil_ep j721e_dst_ep_map[] = {
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/* SA2UL */
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PSIL_SA2UL(0xc000, 1),
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PSIL_SA2UL(0xc001, 1),
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/* PRU_ICSSG0 */
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PSIL_ETHERNET(0xc100),
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PSIL_ETHERNET(0xc101),
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PSIL_ETHERNET(0xc102),
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PSIL_ETHERNET(0xc103),
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PSIL_ETHERNET(0xc104),
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PSIL_ETHERNET(0xc105),
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PSIL_ETHERNET(0xc106),
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PSIL_ETHERNET(0xc107),
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/* PRU_ICSSG1 */
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PSIL_ETHERNET(0xc200),
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PSIL_ETHERNET(0xc201),
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PSIL_ETHERNET(0xc202),
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PSIL_ETHERNET(0xc203),
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PSIL_ETHERNET(0xc204),
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PSIL_ETHERNET(0xc205),
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PSIL_ETHERNET(0xc206),
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PSIL_ETHERNET(0xc207),
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/* PDMA6 (PSIL_PDMA_MCASP_G0) - McASP0-2 */
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PSIL_PDMA_MCASP(0xc400),
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PSIL_PDMA_MCASP(0xc401),
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PSIL_PDMA_MCASP(0xc402),
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/* PDMA7 (PSIL_PDMA_MCASP_G1) - McASP3-11 */
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PSIL_PDMA_MCASP(0xc500),
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PSIL_PDMA_MCASP(0xc501),
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PSIL_PDMA_MCASP(0xc502),
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PSIL_PDMA_MCASP(0xc503),
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PSIL_PDMA_MCASP(0xc504),
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PSIL_PDMA_MCASP(0xc505),
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PSIL_PDMA_MCASP(0xc506),
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PSIL_PDMA_MCASP(0xc507),
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PSIL_PDMA_MCASP(0xc508),
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/* PDMA8 (PDMA_MISC_G0) - SPI0-1 */
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PSIL_PDMA_XY_PKT(0xc600),
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PSIL_PDMA_XY_PKT(0xc601),
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PSIL_PDMA_XY_PKT(0xc602),
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PSIL_PDMA_XY_PKT(0xc603),
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PSIL_PDMA_XY_PKT(0xc604),
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PSIL_PDMA_XY_PKT(0xc605),
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PSIL_PDMA_XY_PKT(0xc606),
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PSIL_PDMA_XY_PKT(0xc607),
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/* PDMA9 (PDMA_MISC_G1) - SPI2-3 */
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PSIL_PDMA_XY_PKT(0xc60c),
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PSIL_PDMA_XY_PKT(0xc60d),
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PSIL_PDMA_XY_PKT(0xc60e),
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PSIL_PDMA_XY_PKT(0xc60f),
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PSIL_PDMA_XY_PKT(0xc610),
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PSIL_PDMA_XY_PKT(0xc611),
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PSIL_PDMA_XY_PKT(0xc612),
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PSIL_PDMA_XY_PKT(0xc613),
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/* PDMA10 (PDMA_MISC_G2) - SPI4-5 */
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PSIL_PDMA_XY_PKT(0xc618),
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PSIL_PDMA_XY_PKT(0xc619),
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PSIL_PDMA_XY_PKT(0xc61a),
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PSIL_PDMA_XY_PKT(0xc61b),
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PSIL_PDMA_XY_PKT(0xc61c),
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PSIL_PDMA_XY_PKT(0xc61d),
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PSIL_PDMA_XY_PKT(0xc61e),
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PSIL_PDMA_XY_PKT(0xc61f),
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/* PDMA11 (PDMA_MISC_G3) */
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||
|
|
PSIL_PDMA_XY_PKT(0xc624),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc625),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc626),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc627),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc628),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc629),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc630),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc63a),
|
||
|
|
/* PDMA13 (PDMA_USART_G0) - UART0-1 */
|
||
|
|
PSIL_PDMA_XY_PKT(0xc700),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc701),
|
||
|
|
/* PDMA14 (PDMA_USART_G1) - UART2-3 */
|
||
|
|
PSIL_PDMA_XY_PKT(0xc702),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc703),
|
||
|
|
/* PDMA15 (PDMA_USART_G2) - UART4-9 */
|
||
|
|
PSIL_PDMA_XY_PKT(0xc704),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc705),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc706),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc707),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc708),
|
||
|
|
PSIL_PDMA_XY_PKT(0xc709),
|
||
|
|
/* CPSW9 */
|
||
|
|
PSIL_ETHERNET(0xca00),
|
||
|
|
PSIL_ETHERNET(0xca01),
|
||
|
|
PSIL_ETHERNET(0xca02),
|
||
|
|
PSIL_ETHERNET(0xca03),
|
||
|
|
PSIL_ETHERNET(0xca04),
|
||
|
|
PSIL_ETHERNET(0xca05),
|
||
|
|
PSIL_ETHERNET(0xca06),
|
||
|
|
PSIL_ETHERNET(0xca07),
|
||
|
|
/* CPSW0 */
|
||
|
|
PSIL_ETHERNET(0xf000),
|
||
|
|
PSIL_ETHERNET(0xf001),
|
||
|
|
PSIL_ETHERNET(0xf002),
|
||
|
|
PSIL_ETHERNET(0xf003),
|
||
|
|
PSIL_ETHERNET(0xf004),
|
||
|
|
PSIL_ETHERNET(0xf005),
|
||
|
|
PSIL_ETHERNET(0xf006),
|
||
|
|
PSIL_ETHERNET(0xf007),
|
||
|
|
/* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
|
||
|
|
PSIL_PDMA_XY_PKT(0xf100),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf101),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf102),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf103),
|
||
|
|
/* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
|
||
|
|
PSIL_PDMA_XY_PKT(0xf200),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf201),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf202),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf203),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf204),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf205),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf206),
|
||
|
|
PSIL_PDMA_XY_PKT(0xf207),
|
||
|
|
/* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
|
||
|
|
PSIL_PDMA_XY_PKT(0xf300),
|
||
|
|
/* SA2UL */
|
||
|
|
PSIL_SA2UL(0xf500, 1),
|
||
|
|
PSIL_SA2UL(0xf501, 1),
|
||
|
|
};
|
||
|
|
|
||
|
|
struct psil_ep_map j721e_ep_map = {
|
||
|
|
.name = "j721e",
|
||
|
|
.src = j721e_src_ep_map,
|
||
|
|
.src_count = ARRAY_SIZE(j721e_src_ep_map),
|
||
|
|
.dst = j721e_dst_ep_map,
|
||
|
|
.dst_count = ARRAY_SIZE(j721e_dst_ep_map),
|
||
|
|
};
|