167 lines
5.3 KiB
C
167 lines
5.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved.
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* Copyright (C) 2022, Advanced Micro Devices, Inc.
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*/
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#ifndef __DMA_XDMA_REGS_H
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#define __DMA_XDMA_REGS_H
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/* The length of register space exposed to host */
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#define XDMA_REG_SPACE_LEN 65536
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/*
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* maximum number of DMA channels for each direction:
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* Host to Card (H2C) or Card to Host (C2H)
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*/
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#define XDMA_MAX_CHANNELS 4
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/*
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* macros to define the number of descriptor blocks can be used in one
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* DMA transfer request.
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* the DMA engine uses a linked list of descriptor blocks that specify the
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* source, destination, and length of the DMA transfers.
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*/
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#define XDMA_DESC_BLOCK_NUM BIT(7)
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#define XDMA_DESC_BLOCK_MASK (XDMA_DESC_BLOCK_NUM - 1)
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/* descriptor definitions */
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#define XDMA_DESC_ADJACENT 32
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#define XDMA_DESC_ADJACENT_MASK (XDMA_DESC_ADJACENT - 1)
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#define XDMA_DESC_ADJACENT_BITS GENMASK(13, 8)
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#define XDMA_DESC_MAGIC 0xad4bUL
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#define XDMA_DESC_MAGIC_BITS GENMASK(31, 16)
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#define XDMA_DESC_FLAGS_BITS GENMASK(7, 0)
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#define XDMA_DESC_STOPPED BIT(0)
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#define XDMA_DESC_COMPLETED BIT(1)
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#define XDMA_DESC_BLEN_BITS 28
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#define XDMA_DESC_BLEN_MAX (BIT(XDMA_DESC_BLEN_BITS) - PAGE_SIZE)
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/* macros to construct the descriptor control word */
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#define XDMA_DESC_CONTROL(adjacent, flag) \
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(FIELD_PREP(XDMA_DESC_MAGIC_BITS, XDMA_DESC_MAGIC) | \
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FIELD_PREP(XDMA_DESC_ADJACENT_BITS, (adjacent) - 1) | \
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FIELD_PREP(XDMA_DESC_FLAGS_BITS, (flag)))
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#define XDMA_DESC_CONTROL_LAST \
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XDMA_DESC_CONTROL(1, XDMA_DESC_STOPPED | XDMA_DESC_COMPLETED)
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/*
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* Descriptor for a single contiguous memory block transfer.
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*
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* Multiple descriptors are linked by means of the next pointer. An additional
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* extra adjacent number gives the amount of extra contiguous descriptors.
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*
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* The descriptors are in root complex memory, and the bytes in the 32-bit
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* words must be in little-endian byte ordering.
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*/
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struct xdma_hw_desc {
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__le32 control;
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__le32 bytes;
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__le64 src_addr;
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__le64 dst_addr;
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__le64 next_desc;
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};
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#define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc)
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#define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
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#define XDMA_DESC_BLOCK_ALIGN 4096
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/*
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* Channel registers
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*/
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#define XDMA_CHAN_IDENTIFIER 0x0
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#define XDMA_CHAN_CONTROL 0x4
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#define XDMA_CHAN_CONTROL_W1S 0x8
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#define XDMA_CHAN_CONTROL_W1C 0xc
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#define XDMA_CHAN_STATUS 0x40
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#define XDMA_CHAN_COMPLETED_DESC 0x48
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#define XDMA_CHAN_ALIGNMENTS 0x4c
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#define XDMA_CHAN_INTR_ENABLE 0x90
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#define XDMA_CHAN_INTR_ENABLE_W1S 0x94
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#define XDMA_CHAN_INTR_ENABLE_W1C 0x9c
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#define XDMA_CHAN_STRIDE 0x100
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#define XDMA_CHAN_H2C_OFFSET 0x0
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#define XDMA_CHAN_C2H_OFFSET 0x1000
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#define XDMA_CHAN_H2C_TARGET 0x0
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#define XDMA_CHAN_C2H_TARGET 0x1
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/* macro to check if channel is available */
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#define XDMA_CHAN_MAGIC 0x1fc0
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#define XDMA_CHAN_CHECK_TARGET(id, target) \
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(((u32)(id) >> 16) == XDMA_CHAN_MAGIC + (target))
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/* bits of the channel control register */
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#define CHAN_CTRL_RUN_STOP BIT(0)
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#define CHAN_CTRL_IE_DESC_STOPPED BIT(1)
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#define CHAN_CTRL_IE_DESC_COMPLETED BIT(2)
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#define CHAN_CTRL_IE_DESC_ALIGN_MISMATCH BIT(3)
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#define CHAN_CTRL_IE_MAGIC_STOPPED BIT(4)
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#define CHAN_CTRL_IE_IDLE_STOPPED BIT(6)
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#define CHAN_CTRL_IE_READ_ERROR GENMASK(13, 9)
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#define CHAN_CTRL_IE_DESC_ERROR GENMASK(23, 19)
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#define CHAN_CTRL_NON_INCR_ADDR BIT(25)
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#define CHAN_CTRL_POLL_MODE_WB BIT(26)
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#define CHAN_CTRL_START (CHAN_CTRL_RUN_STOP | \
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CHAN_CTRL_IE_DESC_STOPPED | \
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CHAN_CTRL_IE_DESC_COMPLETED | \
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CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \
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CHAN_CTRL_IE_MAGIC_STOPPED | \
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CHAN_CTRL_IE_READ_ERROR | \
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CHAN_CTRL_IE_DESC_ERROR)
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/* bits of the channel interrupt enable mask */
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#define CHAN_IM_DESC_ERROR BIT(19)
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#define CHAN_IM_READ_ERROR BIT(9)
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#define CHAN_IM_IDLE_STOPPED BIT(6)
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#define CHAN_IM_MAGIC_STOPPED BIT(4)
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#define CHAN_IM_DESC_COMPLETED BIT(2)
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#define CHAN_IM_DESC_STOPPED BIT(1)
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#define CHAN_IM_ALL (CHAN_IM_DESC_ERROR | CHAN_IM_READ_ERROR | \
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CHAN_IM_IDLE_STOPPED | CHAN_IM_MAGIC_STOPPED | \
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CHAN_IM_DESC_COMPLETED | CHAN_IM_DESC_STOPPED)
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/*
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* Channel SGDMA registers
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*/
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#define XDMA_SGDMA_IDENTIFIER 0x4000
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#define XDMA_SGDMA_DESC_LO 0x4080
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#define XDMA_SGDMA_DESC_HI 0x4084
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#define XDMA_SGDMA_DESC_ADJ 0x4088
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#define XDMA_SGDMA_DESC_CREDIT 0x408c
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/* bits of the SG DMA control register */
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#define XDMA_CTRL_RUN_STOP BIT(0)
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#define XDMA_CTRL_IE_DESC_STOPPED BIT(1)
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#define XDMA_CTRL_IE_DESC_COMPLETED BIT(2)
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#define XDMA_CTRL_IE_DESC_ALIGN_MISMATCH BIT(3)
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#define XDMA_CTRL_IE_MAGIC_STOPPED BIT(4)
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#define XDMA_CTRL_IE_IDLE_STOPPED BIT(6)
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#define XDMA_CTRL_IE_READ_ERROR GENMASK(13, 9)
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#define XDMA_CTRL_IE_DESC_ERROR GENMASK(23, 19)
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#define XDMA_CTRL_NON_INCR_ADDR BIT(25)
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#define XDMA_CTRL_POLL_MODE_WB BIT(26)
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/*
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* interrupt registers
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*/
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#define XDMA_IRQ_IDENTIFIER 0x2000
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#define XDMA_IRQ_USER_INT_EN 0x2004
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#define XDMA_IRQ_USER_INT_EN_W1S 0x2008
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#define XDMA_IRQ_USER_INT_EN_W1C 0x200c
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#define XDMA_IRQ_CHAN_INT_EN 0x2010
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#define XDMA_IRQ_CHAN_INT_EN_W1S 0x2014
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#define XDMA_IRQ_CHAN_INT_EN_W1C 0x2018
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#define XDMA_IRQ_USER_INT_REQ 0x2040
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#define XDMA_IRQ_CHAN_INT_REQ 0x2044
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#define XDMA_IRQ_USER_INT_PEND 0x2048
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#define XDMA_IRQ_CHAN_INT_PEND 0x204c
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#define XDMA_IRQ_USER_VEC_NUM 0x2080
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#define XDMA_IRQ_CHAN_VEC_NUM 0x20a0
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#define XDMA_IRQ_VEC_SHIFT 8
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#endif /* __DMA_XDMA_REGS_H */
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