510 lines
15 KiB
C
510 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* GPIO driver for the WinSystems WS16C48
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* Copyright (C) 2016 William Breathitt Gray
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*/
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#include <linux/bitmap.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define WS16C48_EXTENT 10
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#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
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static unsigned int base[MAX_NUM_WS16C48];
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static unsigned int num_ws16c48;
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module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
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MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
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static unsigned int irq[MAX_NUM_WS16C48];
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static unsigned int num_irq;
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module_param_hw_array(irq, uint, irq, &num_irq, 0);
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MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
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/**
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* struct ws16c48_reg - device register structure
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* @port: Port 0 through 5 I/O
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* @int_pending: Interrupt Pending
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* @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0)
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* @pol_enab_int_id: Interrupt polarity, enable, and ID
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*/
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struct ws16c48_reg {
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u8 port[6];
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u8 int_pending;
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u8 page_lock;
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u8 pol_enab_int_id[3];
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};
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/**
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* struct ws16c48_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @io_state: bit I/O state (whether bit is set to input or output)
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* @out_state: output bits state
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* @lock: synchronization lock to prevent I/O race conditions
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* @irq_mask: I/O bits affected by interrupts
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* @flow_mask: IRQ flow type mask for the respective I/O bits
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* @reg: I/O address offset for the device registers
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*/
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struct ws16c48_gpio {
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struct gpio_chip chip;
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unsigned char io_state[6];
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unsigned char out_state[6];
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raw_spinlock_t lock;
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unsigned long irq_mask;
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unsigned long flow_mask;
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struct ws16c48_reg __iomem *reg;
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};
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static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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if (ws16c48gpio->io_state[port] & mask)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->io_state[port] |= mask;
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ws16c48gpio->out_state[port] &= ~mask;
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return 0;
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}
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static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->io_state[port] &= ~mask;
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if (value)
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ws16c48gpio->out_state[port] |= mask;
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else
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ws16c48gpio->out_state[port] &= ~mask;
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return 0;
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}
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static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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unsigned port_state;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* ensure that GPIO is set for input */
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if (!(ws16c48gpio->io_state[port] & mask)) {
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return -EINVAL;
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}
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port_state = ioread8(ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return !!(port_state & mask);
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}
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static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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size_t index;
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u8 __iomem *port_addr;
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unsigned long port_state;
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/* clear bits array to a clean slate */
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bitmap_zero(bits, chip->ngpio);
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for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
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index = offset / 8;
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port_addr = ws16c48gpio->reg->port + index;
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port_state = ioread8(port_addr) & gpio_mask;
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bitmap_set_value8(bits, port_state, offset);
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}
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return 0;
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}
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static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* ensure that GPIO is set for output */
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if (ws16c48gpio->io_state[port] & mask) {
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return;
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}
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if (value)
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ws16c48gpio->out_state[port] |= mask;
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else
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ws16c48gpio->out_state[port] &= ~mask;
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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size_t index;
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u8 __iomem *port_addr;
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unsigned long bitmask;
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unsigned long flags;
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for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
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index = offset / 8;
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port_addr = ws16c48gpio->reg->port + index;
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/* mask out GPIO configured for input */
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gpio_mask &= ~ws16c48gpio->io_state[index];
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bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* update output state data and set device gpio register */
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ws16c48gpio->out_state[index] &= ~gpio_mask;
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ws16c48gpio->out_state[index] |= bitmask;
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iowrite8(ws16c48gpio->out_state[index], port_addr);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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}
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static void ws16c48_irq_ack(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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unsigned port_state;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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return;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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port_state = ws16c48gpio->irq_mask >> (8*port);
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/* Select Register Page 2; Unlock all I/O ports */
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iowrite8(0x80, &ws16c48gpio->reg->page_lock);
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/* Clear pending interrupt */
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iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port);
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iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static void ws16c48_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned long mask = BIT(offset);
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const unsigned port = offset / 8;
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unsigned long flags;
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unsigned long port_state;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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return;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->irq_mask &= ~mask;
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gpiochip_disable_irq(chip, offset);
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port_state = ws16c48gpio->irq_mask >> (8 * port);
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/* Select Register Page 2; Unlock all I/O ports */
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iowrite8(0x80, &ws16c48gpio->reg->page_lock);
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/* Disable interrupt */
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iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static void ws16c48_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned long mask = BIT(offset);
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const unsigned port = offset / 8;
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unsigned long flags;
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unsigned long port_state;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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return;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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gpiochip_enable_irq(chip, offset);
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ws16c48gpio->irq_mask |= mask;
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port_state = ws16c48gpio->irq_mask >> (8 * port);
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/* Select Register Page 2; Unlock all I/O ports */
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iowrite8(0x80, &ws16c48gpio->reg->page_lock);
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/* Enable interrupt */
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iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned long mask = BIT(offset);
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const unsigned port = offset / 8;
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unsigned long flags;
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unsigned long port_state;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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return -EINVAL;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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switch (flow_type) {
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case IRQ_TYPE_NONE:
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break;
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case IRQ_TYPE_EDGE_RISING:
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ws16c48gpio->flow_mask |= mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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ws16c48gpio->flow_mask &= ~mask;
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break;
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default:
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return -EINVAL;
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}
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port_state = ws16c48gpio->flow_mask >> (8 * port);
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/* Select Register Page 1; Unlock all I/O ports */
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iowrite8(0x40, &ws16c48gpio->reg->page_lock);
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/* Set interrupt polarity */
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iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
|
||
|
|
|
||
|
|
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct irq_chip ws16c48_irqchip = {
|
||
|
|
.name = "ws16c48",
|
||
|
|
.irq_ack = ws16c48_irq_ack,
|
||
|
|
.irq_mask = ws16c48_irq_mask,
|
||
|
|
.irq_unmask = ws16c48_irq_unmask,
|
||
|
|
.irq_set_type = ws16c48_irq_set_type,
|
||
|
|
.flags = IRQCHIP_IMMUTABLE,
|
||
|
|
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
|
||
|
|
{
|
||
|
|
struct ws16c48_gpio *const ws16c48gpio = dev_id;
|
||
|
|
struct gpio_chip *const chip = &ws16c48gpio->chip;
|
||
|
|
struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg;
|
||
|
|
unsigned long int_pending;
|
||
|
|
unsigned long port;
|
||
|
|
unsigned long int_id;
|
||
|
|
unsigned long gpio;
|
||
|
|
|
||
|
|
int_pending = ioread8(®->int_pending) & 0x7;
|
||
|
|
if (!int_pending)
|
||
|
|
return IRQ_NONE;
|
||
|
|
|
||
|
|
/* loop until all pending interrupts are handled */
|
||
|
|
do {
|
||
|
|
for_each_set_bit(port, &int_pending, 3) {
|
||
|
|
int_id = ioread8(reg->pol_enab_int_id + port);
|
||
|
|
for_each_set_bit(gpio, &int_id, 8)
|
||
|
|
generic_handle_domain_irq(chip->irq.domain,
|
||
|
|
gpio + 8*port);
|
||
|
|
}
|
||
|
|
|
||
|
|
int_pending = ioread8(®->int_pending) & 0x7;
|
||
|
|
} while (int_pending);
|
||
|
|
|
||
|
|
return IRQ_HANDLED;
|
||
|
|
}
|
||
|
|
|
||
|
|
#define WS16C48_NGPIO 48
|
||
|
|
static const char *ws16c48_names[WS16C48_NGPIO] = {
|
||
|
|
"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
|
||
|
|
"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
|
||
|
|
"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
|
||
|
|
"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
|
||
|
|
"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
|
||
|
|
"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
|
||
|
|
"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
|
||
|
|
"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
|
||
|
|
"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
|
||
|
|
"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
|
||
|
|
"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
|
||
|
|
"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
|
||
|
|
};
|
||
|
|
|
||
|
|
static int ws16c48_irq_init_hw(struct gpio_chip *gc)
|
||
|
|
{
|
||
|
|
struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
|
||
|
|
|
||
|
|
/* Select Register Page 2; Unlock all I/O ports */
|
||
|
|
iowrite8(0x80, &ws16c48gpio->reg->page_lock);
|
||
|
|
|
||
|
|
/* Disable interrupts for all lines */
|
||
|
|
iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]);
|
||
|
|
iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]);
|
||
|
|
iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]);
|
||
|
|
|
||
|
|
/* Select Register Page 3; Unlock all I/O ports */
|
||
|
|
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ws16c48_probe(struct device *dev, unsigned int id)
|
||
|
|
{
|
||
|
|
struct ws16c48_gpio *ws16c48gpio;
|
||
|
|
const char *const name = dev_name(dev);
|
||
|
|
struct gpio_irq_chip *girq;
|
||
|
|
int err;
|
||
|
|
|
||
|
|
ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
|
||
|
|
if (!ws16c48gpio)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
|
||
|
|
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
|
||
|
|
base[id], base[id] + WS16C48_EXTENT);
|
||
|
|
return -EBUSY;
|
||
|
|
}
|
||
|
|
|
||
|
|
ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
|
||
|
|
if (!ws16c48gpio->reg)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
ws16c48gpio->chip.label = name;
|
||
|
|
ws16c48gpio->chip.parent = dev;
|
||
|
|
ws16c48gpio->chip.owner = THIS_MODULE;
|
||
|
|
ws16c48gpio->chip.base = -1;
|
||
|
|
ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
|
||
|
|
ws16c48gpio->chip.names = ws16c48_names;
|
||
|
|
ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
|
||
|
|
ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
|
||
|
|
ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
|
||
|
|
ws16c48gpio->chip.get = ws16c48_gpio_get;
|
||
|
|
ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
|
||
|
|
ws16c48gpio->chip.set = ws16c48_gpio_set;
|
||
|
|
ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
|
||
|
|
|
||
|
|
girq = &ws16c48gpio->chip.irq;
|
||
|
|
gpio_irq_chip_set_chip(girq, &ws16c48_irqchip);
|
||
|
|
/* This will let us handle the parent IRQ in the driver */
|
||
|
|
girq->parent_handler = NULL;
|
||
|
|
girq->num_parents = 0;
|
||
|
|
girq->parents = NULL;
|
||
|
|
girq->default_type = IRQ_TYPE_NONE;
|
||
|
|
girq->handler = handle_edge_irq;
|
||
|
|
girq->init_hw = ws16c48_irq_init_hw;
|
||
|
|
|
||
|
|
raw_spin_lock_init(&ws16c48gpio->lock);
|
||
|
|
|
||
|
|
err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "GPIO registering failed (%d)\n", err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
|
||
|
|
name, ws16c48gpio);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "IRQ handler registering failed (%d)\n", err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct isa_driver ws16c48_driver = {
|
||
|
|
.probe = ws16c48_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "ws16c48"
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_isa_driver_with_irq(ws16c48_driver, num_ws16c48, num_irq);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
|
||
|
|
MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|