427 lines
12 KiB
C
427 lines
12 KiB
C
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "aldebaran.h"
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#include "amdgpu_reset.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_dpm.h"
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#include "amdgpu_job.h"
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#include "amdgpu_ring.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_xgmi.h"
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static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
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adev->gmc.xgmi.connected_to_cpu))
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return true;
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return false;
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}
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static struct amdgpu_reset_handler *
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aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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struct amdgpu_reset_handler *handler;
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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if (reset_context->method != AMD_RESET_METHOD_NONE) {
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dev_dbg(adev->dev, "Getting reset handler for method %d\n",
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reset_context->method);
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list_for_each_entry(handler, &reset_ctl->reset_handlers,
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handler_list) {
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if (handler->reset_method == reset_context->method)
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return handler;
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}
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}
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if (aldebaran_is_mode2_default(reset_ctl)) {
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list_for_each_entry(handler, &reset_ctl->reset_handlers,
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handler_list) {
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if (handler->reset_method == AMD_RESET_METHOD_MODE2) {
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reset_context->method = AMD_RESET_METHOD_MODE2;
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return handler;
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}
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}
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}
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dev_dbg(adev->dev, "Reset handler not found!\n");
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return NULL;
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}
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static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev)
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{
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int r, i;
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amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
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amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
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for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
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if (!(adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_GFX ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_SDMA))
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continue;
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r = adev->ip_blocks[i].version->funcs->suspend(adev);
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if (r) {
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dev_err(adev->dev,
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"suspend of IP block <%s> failed %d\n",
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adev->ip_blocks[i].version->funcs->name, r);
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return r;
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}
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adev->ip_blocks[i].status.hw = false;
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}
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return r;
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}
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static int
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aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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int r = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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dev_dbg(adev->dev, "Aldebaran prepare hw context\n");
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/* Don't suspend on bare metal if we are not going to HW reset the ASIC */
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if (!amdgpu_sriov_vf(adev))
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r = aldebaran_mode2_suspend_ip(adev);
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return r;
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}
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static void aldebaran_async_reset(struct work_struct *work)
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{
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struct amdgpu_reset_handler *handler;
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struct amdgpu_reset_control *reset_ctl =
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container_of(work, struct amdgpu_reset_control, reset_work);
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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list_for_each_entry(handler, &reset_ctl->reset_handlers,
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handler_list) {
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if (handler->reset_method == reset_ctl->active_reset) {
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dev_dbg(adev->dev, "Resetting device\n");
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handler->do_reset(adev);
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break;
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}
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}
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}
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static int aldebaran_mode2_reset(struct amdgpu_device *adev)
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{
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/* disable BM */
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pci_clear_master(adev->pdev);
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adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev);
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return adev->asic_reset_res;
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}
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static int
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aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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struct list_head *reset_device_list = reset_context->reset_device_list;
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struct amdgpu_device *tmp_adev = NULL;
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int r = 0;
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dev_dbg(adev->dev, "aldebaran perform hw reset\n");
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if (reset_device_list == NULL)
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return -EINVAL;
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if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
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reset_context->hive == NULL) {
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/* Wrong context, return error */
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return -EINVAL;
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}
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list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
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mutex_lock(&tmp_adev->reset_cntl->reset_lock);
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tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;
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}
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/*
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* Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch
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* them together so that they can be completed asynchronously on multiple nodes
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*/
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list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
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/* For XGMI run all resets in parallel to speed up the process */
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if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
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if (!queue_work(system_unbound_wq,
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&tmp_adev->reset_cntl->reset_work))
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r = -EALREADY;
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} else
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r = aldebaran_mode2_reset(tmp_adev);
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if (r) {
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dev_err(tmp_adev->dev,
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"ASIC reset failed with error, %d for drm dev, %s",
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r, adev_to_drm(tmp_adev)->unique);
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break;
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}
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}
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/* For XGMI wait for all resets to complete before proceed */
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if (!r) {
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list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
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if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
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flush_work(&tmp_adev->reset_cntl->reset_work);
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r = tmp_adev->asic_reset_res;
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if (r)
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break;
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}
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}
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}
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list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
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mutex_unlock(&tmp_adev->reset_cntl->reset_lock);
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tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;
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}
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return r;
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}
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static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)
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{
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struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM];
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struct amdgpu_firmware_info *ucode;
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struct amdgpu_ip_block *cmn_block;
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int ucode_count = 0;
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int i, r;
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dev_dbg(adev->dev, "Reloading ucodes after reset\n");
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for (i = 0; i < adev->firmware.max_ucodes; i++) {
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ucode = &adev->firmware.ucode[i];
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if (!ucode->fw)
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continue;
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switch (ucode->ucode_id) {
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case AMDGPU_UCODE_ID_SDMA0:
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case AMDGPU_UCODE_ID_SDMA1:
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case AMDGPU_UCODE_ID_SDMA2:
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case AMDGPU_UCODE_ID_SDMA3:
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case AMDGPU_UCODE_ID_SDMA4:
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case AMDGPU_UCODE_ID_SDMA5:
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case AMDGPU_UCODE_ID_SDMA6:
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case AMDGPU_UCODE_ID_SDMA7:
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case AMDGPU_UCODE_ID_CP_MEC1:
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case AMDGPU_UCODE_ID_CP_MEC1_JT:
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case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
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case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
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case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
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case AMDGPU_UCODE_ID_RLC_G:
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ucode_list[ucode_count++] = ucode;
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break;
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default:
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break;
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}
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}
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/* Reinit NBIF block */
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cmn_block =
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amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON);
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if (unlikely(!cmn_block)) {
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dev_err(adev->dev, "Failed to get BIF handle\n");
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return -EINVAL;
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}
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r = cmn_block->version->funcs->resume(adev);
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if (r)
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return r;
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/* Reinit GFXHUB */
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adev->gfxhub.funcs->init(adev);
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r = adev->gfxhub.funcs->gart_enable(adev);
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if (r) {
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dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
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return r;
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}
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/* Reload GFX firmware */
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r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count);
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if (r) {
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dev_err(adev->dev, "GFX ucode load failed after reset\n");
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return r;
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}
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/* Resume RLC, FW needs RLC alive to complete reset process */
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adev->gfx.rlc.funcs->resume(adev);
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/* Wait for FW reset event complete */
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r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);
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if (r) {
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dev_err(adev->dev,
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"Failed to get response from firmware after reset\n");
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return r;
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}
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (!(adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_GFX ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_SDMA))
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continue;
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r = adev->ip_blocks[i].version->funcs->resume(adev);
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if (r) {
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dev_err(adev->dev,
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"resume of IP block <%s> failed %d\n",
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adev->ip_blocks[i].version->funcs->name, r);
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return r;
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}
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adev->ip_blocks[i].status.hw = true;
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}
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (!(adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_GFX ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_SDMA ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_COMMON))
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continue;
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if (adev->ip_blocks[i].version->funcs->late_init) {
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r = adev->ip_blocks[i].version->funcs->late_init(
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(void *)adev);
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if (r) {
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dev_err(adev->dev,
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"late_init of IP block <%s> failed %d after reset\n",
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adev->ip_blocks[i].version->funcs->name,
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r);
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return r;
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}
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}
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adev->ip_blocks[i].status.late_initialized = true;
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}
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amdgpu_ras_set_error_query_ready(adev, true);
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amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
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amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
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return r;
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}
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static int
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aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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struct list_head *reset_device_list = reset_context->reset_device_list;
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struct amdgpu_device *tmp_adev = NULL;
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int r;
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if (reset_device_list == NULL)
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return -EINVAL;
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if (reset_context->reset_req_dev->ip_versions[MP1_HWIP][0] ==
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IP_VERSION(13, 0, 2) &&
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reset_context->hive == NULL) {
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/* Wrong context, return error */
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return -EINVAL;
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}
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list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
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dev_info(tmp_adev->dev,
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|
"GPU reset succeeded, trying to resume\n");
|
||
|
|
r = aldebaran_mode2_restore_ip(tmp_adev);
|
||
|
|
if (r)
|
||
|
|
goto end;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Add this ASIC as tracked as reset was already
|
||
|
|
* complete successfully.
|
||
|
|
*/
|
||
|
|
amdgpu_register_gpu_instance(tmp_adev);
|
||
|
|
|
||
|
|
/* Resume RAS */
|
||
|
|
amdgpu_ras_resume(tmp_adev);
|
||
|
|
|
||
|
|
/* Update PSP FW topology after reset */
|
||
|
|
if (reset_context->hive &&
|
||
|
|
tmp_adev->gmc.xgmi.num_physical_nodes > 1)
|
||
|
|
r = amdgpu_xgmi_update_topology(reset_context->hive,
|
||
|
|
tmp_adev);
|
||
|
|
|
||
|
|
if (!r) {
|
||
|
|
amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
|
||
|
|
|
||
|
|
r = amdgpu_ib_ring_tests(tmp_adev);
|
||
|
|
if (r) {
|
||
|
|
dev_err(tmp_adev->dev,
|
||
|
|
"ib ring test failed (%d).\n", r);
|
||
|
|
r = -EAGAIN;
|
||
|
|
tmp_adev->asic_reset_res = r;
|
||
|
|
goto end;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
end:
|
||
|
|
return r;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct amdgpu_reset_handler aldebaran_mode2_handler = {
|
||
|
|
.reset_method = AMD_RESET_METHOD_MODE2,
|
||
|
|
.prepare_env = NULL,
|
||
|
|
.prepare_hwcontext = aldebaran_mode2_prepare_hwcontext,
|
||
|
|
.perform_reset = aldebaran_mode2_perform_reset,
|
||
|
|
.restore_hwcontext = aldebaran_mode2_restore_hwcontext,
|
||
|
|
.restore_env = NULL,
|
||
|
|
.do_reset = aldebaran_mode2_reset,
|
||
|
|
};
|
||
|
|
|
||
|
|
int aldebaran_reset_init(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
struct amdgpu_reset_control *reset_ctl;
|
||
|
|
|
||
|
|
reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
|
||
|
|
if (!reset_ctl)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
reset_ctl->handle = adev;
|
||
|
|
reset_ctl->async_reset = aldebaran_async_reset;
|
||
|
|
reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
|
||
|
|
reset_ctl->get_reset_handler = aldebaran_get_reset_handler;
|
||
|
|
|
||
|
|
INIT_LIST_HEAD(&reset_ctl->reset_handlers);
|
||
|
|
INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
|
||
|
|
/* Only mode2 is handled through reset control now */
|
||
|
|
amdgpu_reset_add_handler(reset_ctl, &aldebaran_mode2_handler);
|
||
|
|
|
||
|
|
adev->reset_cntl = reset_ctl;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int aldebaran_reset_fini(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
kfree(adev->reset_cntl);
|
||
|
|
adev->reset_cntl = NULL;
|
||
|
|
return 0;
|
||
|
|
}
|