275 lines
8.0 KiB
C
275 lines
8.0 KiB
C
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "umc_v6_7.h"
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static int amdgpu_umc_convert_error_address(struct amdgpu_device *adev,
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struct ras_err_data *err_data, uint64_t err_addr,
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uint32_t ch_inst, uint32_t umc_inst)
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{
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switch (adev->ip_versions[UMC_HWIP][0]) {
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case IP_VERSION(6, 7, 0):
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umc_v6_7_convert_error_address(adev,
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err_data, err_addr, ch_inst, umc_inst);
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break;
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default:
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dev_warn(adev->dev,
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"UMC address to Physical address translation is not supported\n");
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return AMDGPU_RAS_FAIL;
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}
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return AMDGPU_RAS_SUCCESS;
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}
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int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,
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uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst)
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{
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struct ras_err_data err_data = {0, 0, 0, NULL};
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int ret = AMDGPU_RAS_FAIL;
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err_data.err_addr =
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kcalloc(adev->umc.max_ras_err_cnt_per_query,
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sizeof(struct eeprom_table_record), GFP_KERNEL);
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if (!err_data.err_addr) {
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dev_warn(adev->dev,
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"Failed to alloc memory for umc error record in MCA notifier!\n");
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return AMDGPU_RAS_FAIL;
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}
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/*
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* Translate UMC channel address to Physical address
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*/
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ret = amdgpu_umc_convert_error_address(adev, &err_data, err_addr,
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ch_inst, umc_inst);
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if (ret)
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goto out;
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if (amdgpu_bad_page_threshold != 0) {
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amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
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err_data.err_addr_cnt);
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amdgpu_ras_save_bad_pages(adev, NULL);
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}
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out:
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kfree(err_data.err_addr);
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return ret;
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}
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static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
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void *ras_error_status,
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struct amdgpu_iv_entry *entry,
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bool reset)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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int ret = 0;
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kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
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ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc));
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if (ret == -EOPNOTSUPP) {
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if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
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adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
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adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status);
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if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
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adev->umc.ras->ras_block.hw_ops->query_ras_error_address &&
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adev->umc.max_ras_err_cnt_per_query) {
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err_data->err_addr =
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kcalloc(adev->umc.max_ras_err_cnt_per_query,
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sizeof(struct eeprom_table_record), GFP_KERNEL);
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/* still call query_ras_error_address to clear error status
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* even NOMEM error is encountered
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*/
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if(!err_data->err_addr)
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dev_warn(adev->dev, "Failed to alloc memory for "
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"umc error address record!\n");
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/* umc query_ras_error_address is also responsible for clearing
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* error status
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*/
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adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status);
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}
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} else if (!ret) {
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if (adev->umc.ras &&
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adev->umc.ras->ecc_info_query_ras_error_count)
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adev->umc.ras->ecc_info_query_ras_error_count(adev, ras_error_status);
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if (adev->umc.ras &&
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adev->umc.ras->ecc_info_query_ras_error_address &&
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adev->umc.max_ras_err_cnt_per_query) {
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err_data->err_addr =
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kcalloc(adev->umc.max_ras_err_cnt_per_query,
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sizeof(struct eeprom_table_record), GFP_KERNEL);
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/* still call query_ras_error_address to clear error status
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* even NOMEM error is encountered
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*/
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if(!err_data->err_addr)
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dev_warn(adev->dev, "Failed to alloc memory for "
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"umc error address record!\n");
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/* umc query_ras_error_address is also responsible for clearing
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* error status
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*/
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adev->umc.ras->ecc_info_query_ras_error_address(adev, ras_error_status);
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}
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}
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/* only uncorrectable error needs gpu reset */
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if (err_data->ue_count) {
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dev_info(adev->dev, "%ld uncorrectable hardware errors "
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"detected in UMC block\n",
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err_data->ue_count);
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if ((amdgpu_bad_page_threshold != 0) &&
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err_data->err_addr_cnt) {
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amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
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err_data->err_addr_cnt);
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amdgpu_ras_save_bad_pages(adev, &(err_data->ue_count));
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amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
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if (con->update_channel_flag == true) {
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amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
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con->update_channel_flag = false;
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}
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}
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if (reset)
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amdgpu_ras_reset_gpu(adev);
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}
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kfree(err_data->err_addr);
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return AMDGPU_RAS_SUCCESS;
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}
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int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset)
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{
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int ret = AMDGPU_RAS_SUCCESS;
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if (!amdgpu_sriov_vf(adev)) {
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if (!adev->gmc.xgmi.connected_to_cpu) {
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struct ras_err_data err_data = {0, 0, 0, NULL};
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struct ras_common_if head = {
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.block = AMDGPU_RAS_BLOCK__UMC,
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};
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struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
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ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset);
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if (ret == AMDGPU_RAS_SUCCESS && obj) {
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obj->err_data.ue_count += err_data.ue_count;
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obj->err_data.ce_count += err_data.ce_count;
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}
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} else if (reset) {
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/* MCA poison handler is only responsible for GPU reset,
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* let MCA notifier do page retirement.
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*/
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kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
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amdgpu_ras_reset_gpu(adev);
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}
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} else {
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if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
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adev->virt.ops->ras_poison_handler(adev);
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else
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dev_warn(adev->dev,
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"No ras_poison_handler interface in SRIOV!\n");
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}
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return ret;
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}
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int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
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void *ras_error_status,
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struct amdgpu_iv_entry *entry)
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{
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return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, true);
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}
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int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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int r;
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r = amdgpu_ras_block_late_init(adev, ras_block);
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if (r)
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return r;
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if (amdgpu_ras_is_supported(adev, ras_block->block)) {
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r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
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if (r)
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goto late_fini;
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}
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/* ras init of specific umc version */
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if (adev->umc.ras &&
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adev->umc.ras->err_cnt_init)
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adev->umc.ras->err_cnt_init(adev);
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return 0;
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late_fini:
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amdgpu_ras_block_late_fini(adev, ras_block);
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return r;
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}
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int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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struct ras_common_if *ras_if = adev->umc.ras_if;
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struct ras_dispatch_if ih_data = {
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.entry = entry,
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};
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if (!ras_if)
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return 0;
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ih_data.head = *ras_if;
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amdgpu_ras_interrupt_dispatch(adev, &ih_data);
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return 0;
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}
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void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
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uint64_t err_addr,
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uint64_t retired_page,
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uint32_t channel_index,
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uint32_t umc_inst)
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{
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struct eeprom_table_record *err_rec =
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&err_data->err_addr[err_data->err_addr_cnt];
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err_rec->address = err_addr;
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/* page frame address is saved */
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err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
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err_rec->ts = (uint64_t)ktime_get_real_seconds();
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err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
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err_rec->cu = 0;
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err_rec->mem_channel = channel_index;
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err_rec->mcumc_id = umc_inst;
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err_data->err_addr_cnt++;
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}
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