443 lines
17 KiB
C
443 lines
17 KiB
C
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright 2014-2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/err.h>
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#include <linux/fs.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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#include <linux/compat.h>
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#include <uapi/linux/kfd_ioctl.h>
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#include <linux/time.h>
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#include "kfd_priv.h"
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#include <linux/mm.h>
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#include <linux/mman.h>
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#include <linux/processor.h>
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/*
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* The primary memory I/O features being added for revisions of gfxip
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* beyond 7.0 (Kaveri) are:
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*
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* Access to ATC/IOMMU mapped memory w/ associated extension of VA to 48b
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*
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* “Flat” shader memory access – These are new shader vector memory
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* operations that do not reference a T#/V# so a “pointer” is what is
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* sourced from the vector gprs for direct access to memory.
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* This pointer space has the Shared(LDS) and Private(Scratch) memory
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* mapped into this pointer space as apertures.
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* The hardware then determines how to direct the memory request
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* based on what apertures the request falls in.
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*
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* Unaligned support and alignment check
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*
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*
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* System Unified Address - SUA
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*
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* The standard usage for GPU virtual addresses are that they are mapped by
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* a set of page tables we call GPUVM and these page tables are managed by
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* a combination of vidMM/driver software components. The current virtual
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* address (VA) range for GPUVM is 40b.
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*
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* As of gfxip7.1 and beyond we’re adding the ability for compute memory
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* clients (CP/RLC, DMA, SHADER(ifetch, scalar, and vector ops)) to access
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* the same page tables used by host x86 processors and that are managed by
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* the operating system. This is via a technique and hardware called ATC/IOMMU.
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* The GPU has the capability of accessing both the GPUVM and ATC address
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* spaces for a given VMID (process) simultaneously and we call this feature
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* system unified address (SUA).
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*
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* There are three fundamental address modes of operation for a given VMID
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* (process) on the GPU:
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*
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* HSA64 – 64b pointers and the default address space is ATC
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* HSA32 – 32b pointers and the default address space is ATC
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* GPUVM – 64b pointers and the default address space is GPUVM (driver
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* model mode)
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*
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*
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* HSA64 - ATC/IOMMU 64b
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*
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* A 64b pointer in the AMD64/IA64 CPU architecture is not fully utilized
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* by the CPU so an AMD CPU can only access the high area
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* (VA[63:47] == 0x1FFFF) and low area (VA[63:47 == 0) of the address space
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* so the actual VA carried to translation is 48b. There is a “hole” in
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* the middle of the 64b VA space.
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*
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* The GPU not only has access to all of the CPU accessible address space via
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* ATC/IOMMU, but it also has access to the GPUVM address space. The “system
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* unified address” feature (SUA) is the mapping of GPUVM and ATC address
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* spaces into a unified pointer space. The method we take for 64b mode is
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* to map the full 40b GPUVM address space into the hole of the 64b address
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* space.
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* The GPUVM_Base/GPUVM_Limit defines the aperture in the 64b space where we
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* direct requests to be translated via GPUVM page tables instead of the
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* IOMMU path.
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*
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*
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* 64b to 49b Address conversion
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*
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* Note that there are still significant portions of unused regions (holes)
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* in the 64b address space even for the GPU. There are several places in
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* the pipeline (sw and hw), we wish to compress the 64b virtual address
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* to a 49b address. This 49b address is constituted of an “ATC” bit
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* plus a 48b virtual address. This 49b address is what is passed to the
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* translation hardware. ATC==0 means the 48b address is a GPUVM address
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* (max of 2^40 – 1) intended to be translated via GPUVM page tables.
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* ATC==1 means the 48b address is intended to be translated via IOMMU
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* page tables.
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*
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* A 64b pointer is compared to the apertures that are defined (Base/Limit), in
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* this case the GPUVM aperture (red) is defined and if a pointer falls in this
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* aperture, we subtract the GPUVM_Base address and set the ATC bit to zero
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* as part of the 64b to 49b conversion.
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*
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* Where this 64b to 49b conversion is done is a function of the usage.
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* Most GPU memory access is via memory objects where the driver builds
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* a descriptor which consists of a base address and a memory access by
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* the GPU usually consists of some kind of an offset or Cartesian coordinate
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* that references this memory descriptor. This is the case for shader
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* instructions that reference the T# or V# constants, or for specified
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* locations of assets (ex. the shader program location). In these cases
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* the driver is what handles the 64b to 49b conversion and the base
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* address in the descriptor (ex. V# or T# or shader program location)
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* is defined as a 48b address w/ an ATC bit. For this usage a given
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* memory object cannot straddle multiple apertures in the 64b address
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* space. For example a shader program cannot jump in/out between ATC
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* and GPUVM space.
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*
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* In some cases we wish to pass a 64b pointer to the GPU hardware and
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* the GPU hw does the 64b to 49b conversion before passing memory
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* requests to the cache/memory system. This is the case for the
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* S_LOAD and FLAT_* shader memory instructions where we have 64b pointers
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* in scalar and vector GPRs respectively.
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*
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* In all cases (no matter where the 64b -> 49b conversion is done), the gfxip
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* hardware sends a 48b address along w/ an ATC bit, to the memory controller
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* on the memory request interfaces.
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*
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* <client>_MC_rdreq_atc // read request ATC bit
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*
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* 0 : <client>_MC_rdreq_addr is a GPUVM VA
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*
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* 1 : <client>_MC_rdreq_addr is a ATC VA
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*
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*
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* “Spare” aperture (APE1)
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*
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* We use the GPUVM aperture to differentiate ATC vs. GPUVM, but we also use
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* apertures to set the Mtype field for S_LOAD/FLAT_* ops which is input to the
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* config tables for setting cache policies. The “spare” (APE1) aperture is
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* motivated by getting a different Mtype from the default.
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* The default aperture isn’t an actual base/limit aperture; it is just the
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* address space that doesn’t hit any defined base/limit apertures.
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* The following diagram is a complete picture of the gfxip7.x SUA apertures.
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* The APE1 can be placed either below or above
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* the hole (cannot be in the hole).
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*
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*
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* General Aperture definitions and rules
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*
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* An aperture register definition consists of a Base, Limit, Mtype, and
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* usually an ATC bit indicating which translation tables that aperture uses.
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* In all cases (for SUA and DUA apertures discussed later), aperture base
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* and limit definitions are 64KB aligned.
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*
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* <ape>_Base[63:0] = { <ape>_Base_register[63:16], 0x0000 }
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*
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* <ape>_Limit[63:0] = { <ape>_Limit_register[63:16], 0xFFFF }
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*
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* The base and limit are considered inclusive to an aperture so being
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* inside an aperture means (address >= Base) AND (address <= Limit).
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*
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* In no case is a payload that straddles multiple apertures expected to work.
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* For example a load_dword_x4 that starts in one aperture and ends in another,
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* does not work. For the vector FLAT_* ops we have detection capability in
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* the shader for reporting a “memory violation” back to the
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* SQ block for use in traps.
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* A memory violation results when an op falls into the hole,
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* or a payload straddles multiple apertures. The S_LOAD instruction
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* does not have this detection.
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*
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* Apertures cannot overlap.
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*
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*
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*
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* HSA32 - ATC/IOMMU 32b
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*
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* For HSA32 mode, the pointers are interpreted as 32 bits and use a single GPR
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* instead of two for the S_LOAD and FLAT_* ops. The entire GPUVM space of 40b
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* will not fit so there is only partial visibility to the GPUVM
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* space (defined by the aperture) for S_LOAD and FLAT_* ops.
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* There is no spare (APE1) aperture for HSA32 mode.
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*
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*
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* GPUVM 64b mode (driver model)
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*
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* This mode is related to HSA64 in that the difference really is that
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* the default aperture is GPUVM (ATC==0) and not ATC space.
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* We have gfxip7.x hardware that has FLAT_* and S_LOAD support for
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* SUA GPUVM mode, but does not support HSA32/HSA64.
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*
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*
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* Device Unified Address - DUA
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*
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* Device unified address (DUA) is the name of the feature that maps the
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* Shared(LDS) memory and Private(Scratch) memory into the overall address
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* space for use by the new FLAT_* vector memory ops. The Shared and
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* Private memories are mapped as apertures into the address space,
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* and the hardware detects when a FLAT_* memory request is to be redirected
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* to the LDS or Scratch memory when it falls into one of these apertures.
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* Like the SUA apertures, the Shared/Private apertures are 64KB aligned and
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* the base/limit is “in” the aperture. For both HSA64 and GPUVM SUA modes,
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* the Shared/Private apertures are always placed in a limited selection of
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* options in the hole of the 64b address space. For HSA32 mode, the
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* Shared/Private apertures can be placed anywhere in the 32b space
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* except at 0.
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*
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*
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* HSA64 Apertures for FLAT_* vector ops
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*
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* For HSA64 SUA mode, the Shared and Private apertures are always placed
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* in the hole w/ a limited selection of possible locations. The requests
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* that fall in the private aperture are expanded as a function of the
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* work-item id (tid) and redirected to the location of the
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* “hidden private memory”. The hidden private can be placed in either GPUVM
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* or ATC space. The addresses that fall in the shared aperture are
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* re-directed to the on-chip LDS memory hardware.
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*
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*
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* HSA32 Apertures for FLAT_* vector ops
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*
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* In HSA32 mode, the Private and Shared apertures can be placed anywhere
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* in the 32b space except at 0 (Private or Shared Base at zero disables
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* the apertures). If the base address of the apertures are non-zero
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* (ie apertures exists), the size is always 64KB.
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*
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*
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* GPUVM Apertures for FLAT_* vector ops
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*
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* In GPUVM mode, the Shared/Private apertures are specified identically
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* to HSA64 mode where they are always in the hole at a limited selection
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* of locations.
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*
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*
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* Aperture Definitions for SUA and DUA
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*
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* The interpretation of the aperture register definitions for a given
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* VMID is a function of the “SUA Mode” which is one of HSA64, HSA32, or
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* GPUVM64 discussed in previous sections. The mode is first decoded, and
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* then the remaining register decode is a function of the mode.
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*
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*
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* SUA Mode Decode
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*
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* For the S_LOAD and FLAT_* shader operations, the SUA mode is decoded from
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* the COMPUTE_DISPATCH_INITIATOR:DATA_ATC bit and
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* the SH_MEM_CONFIG:PTR32 bits.
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*
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* COMPUTE_DISPATCH_INITIATOR:DATA_ATC SH_MEM_CONFIG:PTR32 Mode
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*
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* 1 0 HSA64
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*
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* 1 1 HSA32
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*
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* 0 X GPUVM64
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*
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* In general the hardware will ignore the PTR32 bit and treat
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* as “0” whenever DATA_ATC = “0”, but sw should set PTR32=0
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* when DATA_ATC=0.
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*
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* The DATA_ATC bit is only set for compute dispatches.
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* All “Draw” dispatches are hardcoded to GPUVM64 mode
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* for FLAT_* / S_LOAD operations.
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*/
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#define MAKE_GPUVM_APP_BASE_VI(gpu_num) \
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(((uint64_t)(gpu_num) << 61) + 0x1000000000000L)
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#define MAKE_GPUVM_APP_LIMIT(base, size) \
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(((uint64_t)(base) & 0xFFFFFF0000000000UL) + (size) - 1)
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#define MAKE_SCRATCH_APP_BASE_VI() \
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(((uint64_t)(0x1UL) << 61) + 0x100000000L)
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#define MAKE_SCRATCH_APP_LIMIT(base) \
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(((uint64_t)base & 0xFFFFFFFF00000000UL) | 0xFFFFFFFF)
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#define MAKE_LDS_APP_BASE_VI() \
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(((uint64_t)(0x1UL) << 61) + 0x0)
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#define MAKE_LDS_APP_LIMIT(base) \
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(((uint64_t)(base) & 0xFFFFFFFF00000000UL) | 0xFFFFFFFF)
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/* On GFXv9 the LDS and scratch apertures are programmed independently
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* using the high 16 bits of the 64-bit virtual address. They must be
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* in the hole, which will be the case as long as the high 16 bits are
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* not 0.
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*
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* The aperture sizes are still 4GB implicitly.
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*
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* A GPUVM aperture is not applicable on GFXv9.
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*/
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#define MAKE_LDS_APP_BASE_V9() ((uint64_t)(0x1UL) << 48)
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#define MAKE_SCRATCH_APP_BASE_V9() ((uint64_t)(0x2UL) << 48)
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/* User mode manages most of the SVM aperture address space. The low
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* 16MB are reserved for kernel use (CWSR trap handler and kernel IB
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* for now).
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*/
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#define SVM_USER_BASE (u64)(KFD_CWSR_TBA_TMA_SIZE + 2*PAGE_SIZE)
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#define SVM_CWSR_BASE (SVM_USER_BASE - KFD_CWSR_TBA_TMA_SIZE)
|
|||
|
|
#define SVM_IB_BASE (SVM_CWSR_BASE - PAGE_SIZE)
|
|||
|
|
|
|||
|
|
static void kfd_init_apertures_vi(struct kfd_process_device *pdd, uint8_t id)
|
|||
|
|
{
|
|||
|
|
/*
|
|||
|
|
* node id couldn't be 0 - the three MSB bits of
|
|||
|
|
* aperture shouldn't be 0
|
|||
|
|
*/
|
|||
|
|
pdd->lds_base = MAKE_LDS_APP_BASE_VI();
|
|||
|
|
pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
|
|||
|
|
|
|||
|
|
if (!pdd->dev->use_iommu_v2) {
|
|||
|
|
/* dGPUs: SVM aperture starting at 0
|
|||
|
|
* with small reserved space for kernel.
|
|||
|
|
* Set them to CANONICAL addresses.
|
|||
|
|
*/
|
|||
|
|
pdd->gpuvm_base = SVM_USER_BASE;
|
|||
|
|
pdd->gpuvm_limit =
|
|||
|
|
pdd->dev->shared_resources.gpuvm_size - 1;
|
|||
|
|
} else {
|
|||
|
|
/* set them to non CANONICAL addresses, and no SVM is
|
|||
|
|
* allocated.
|
|||
|
|
*/
|
|||
|
|
pdd->gpuvm_base = MAKE_GPUVM_APP_BASE_VI(id + 1);
|
|||
|
|
pdd->gpuvm_limit = MAKE_GPUVM_APP_LIMIT(pdd->gpuvm_base,
|
|||
|
|
pdd->dev->shared_resources.gpuvm_size);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
pdd->scratch_base = MAKE_SCRATCH_APP_BASE_VI();
|
|||
|
|
pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id)
|
|||
|
|
{
|
|||
|
|
pdd->lds_base = MAKE_LDS_APP_BASE_V9();
|
|||
|
|
pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
|
|||
|
|
|
|||
|
|
/* Raven needs SVM to support graphic handle, etc. Leave the small
|
|||
|
|
* reserved space before SVM on Raven as well, even though we don't
|
|||
|
|
* have to.
|
|||
|
|
* Set gpuvm_base and gpuvm_limit to CANONICAL addresses so that they
|
|||
|
|
* are used in Thunk to reserve SVM.
|
|||
|
|
*/
|
|||
|
|
pdd->gpuvm_base = SVM_USER_BASE;
|
|||
|
|
pdd->gpuvm_limit =
|
|||
|
|
pdd->dev->shared_resources.gpuvm_size - 1;
|
|||
|
|
|
|||
|
|
pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9();
|
|||
|
|
pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
int kfd_init_apertures(struct kfd_process *process)
|
|||
|
|
{
|
|||
|
|
uint8_t id = 0;
|
|||
|
|
struct kfd_dev *dev;
|
|||
|
|
struct kfd_process_device *pdd;
|
|||
|
|
|
|||
|
|
/*Iterating over all devices*/
|
|||
|
|
while (kfd_topology_enum_kfd_devices(id, &dev) == 0) {
|
|||
|
|
if (!dev || kfd_devcgroup_check_permission(dev)) {
|
|||
|
|
/* Skip non GPU devices and devices to which the
|
|||
|
|
* current process have no access to. Access can be
|
|||
|
|
* limited by placing the process in a specific
|
|||
|
|
* cgroup hierarchy
|
|||
|
|
*/
|
|||
|
|
id++;
|
|||
|
|
continue;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
pdd = kfd_create_process_device_data(dev, process);
|
|||
|
|
if (!pdd) {
|
|||
|
|
pr_err("Failed to create process device data\n");
|
|||
|
|
return -ENOMEM;
|
|||
|
|
}
|
|||
|
|
/*
|
|||
|
|
* For 64 bit process apertures will be statically reserved in
|
|||
|
|
* the x86_64 non canonical process address space
|
|||
|
|
* amdkfd doesn't currently support apertures for 32 bit process
|
|||
|
|
*/
|
|||
|
|
if (process->is_32bit_user_mode) {
|
|||
|
|
pdd->lds_base = pdd->lds_limit = 0;
|
|||
|
|
pdd->gpuvm_base = pdd->gpuvm_limit = 0;
|
|||
|
|
pdd->scratch_base = pdd->scratch_limit = 0;
|
|||
|
|
} else {
|
|||
|
|
switch (dev->adev->asic_type) {
|
|||
|
|
case CHIP_KAVERI:
|
|||
|
|
case CHIP_HAWAII:
|
|||
|
|
case CHIP_CARRIZO:
|
|||
|
|
case CHIP_TONGA:
|
|||
|
|
case CHIP_FIJI:
|
|||
|
|
case CHIP_POLARIS10:
|
|||
|
|
case CHIP_POLARIS11:
|
|||
|
|
case CHIP_POLARIS12:
|
|||
|
|
case CHIP_VEGAM:
|
|||
|
|
kfd_init_apertures_vi(pdd, id);
|
|||
|
|
break;
|
|||
|
|
default:
|
|||
|
|
if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1))
|
|||
|
|
kfd_init_apertures_v9(pdd, id);
|
|||
|
|
else {
|
|||
|
|
WARN(1, "Unexpected ASIC family %u",
|
|||
|
|
dev->adev->asic_type);
|
|||
|
|
return -EINVAL;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (!dev->use_iommu_v2) {
|
|||
|
|
/* dGPUs: the reserved space for kernel
|
|||
|
|
* before SVM
|
|||
|
|
*/
|
|||
|
|
pdd->qpd.cwsr_base = SVM_CWSR_BASE;
|
|||
|
|
pdd->qpd.ib_base = SVM_IB_BASE;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
dev_dbg(kfd_device, "node id %u\n", id);
|
|||
|
|
dev_dbg(kfd_device, "gpu id %u\n", pdd->dev->id);
|
|||
|
|
dev_dbg(kfd_device, "lds_base %llX\n", pdd->lds_base);
|
|||
|
|
dev_dbg(kfd_device, "lds_limit %llX\n", pdd->lds_limit);
|
|||
|
|
dev_dbg(kfd_device, "gpuvm_base %llX\n", pdd->gpuvm_base);
|
|||
|
|
dev_dbg(kfd_device, "gpuvm_limit %llX\n", pdd->gpuvm_limit);
|
|||
|
|
dev_dbg(kfd_device, "scratch_base %llX\n", pdd->scratch_base);
|
|||
|
|
dev_dbg(kfd_device, "scratch_limit %llX\n", pdd->scratch_limit);
|
|||
|
|
|
|||
|
|
id++;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return 0;
|
|||
|
|
}
|