160 lines
5.4 KiB
C
160 lines
5.4 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_HWSS_DCN20_H__
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#define __DC_HWSS_DCN20_H__
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#include "hw_sequencer_private.h"
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bool dcn20_set_blend_lut(
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struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
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bool dcn20_set_shaper_3dlut(
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struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
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void dcn20_program_front_end_for_ctx(
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struct dc *dc,
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struct dc_state *context);
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void dcn20_post_unlock_program_front_end(
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struct dc *dc,
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struct dc_state *context);
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void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
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void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
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bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
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const struct dc_stream_state *stream);
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void dcn20_program_output_csc(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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enum dc_color_space colorspace,
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uint16_t *matrix,
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int opp_id);
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void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
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void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
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struct dc_link_settings *link_settings);
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void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void dcn20_disable_pixel_data(
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struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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bool blank);
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void dcn20_blank_pixel_data(
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struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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bool blank);
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void dcn20_pipe_control_lock(
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struct dc *dc,
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struct pipe_ctx *pipe,
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bool lock);
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void dcn20_prepare_bandwidth(
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struct dc *dc,
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struct dc_state *context);
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void dcn20_optimize_bandwidth(
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struct dc *dc,
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struct dc_state *context);
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bool dcn20_update_bandwidth(
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struct dc *dc,
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struct dc_state *context);
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void dcn20_reset_hw_ctx_wrap(
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struct dc *dc,
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struct dc_state *context);
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enum dc_status dcn20_enable_stream_timing(
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struct pipe_ctx *pipe_ctx,
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struct dc_state *context,
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struct dc *dc);
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void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void dcn20_init_blank(
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struct dc *dc,
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struct timing_generator *tg);
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void dcn20_disable_vga(
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struct dce_hwseq *hws);
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void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void dcn20_enable_power_gating_plane(
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struct dce_hwseq *hws,
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bool enable);
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void dcn20_dpp_pg_control(
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struct dce_hwseq *hws,
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unsigned int dpp_inst,
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bool power_on);
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void dcn20_hubp_pg_control(
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struct dce_hwseq *hws,
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unsigned int hubp_inst,
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bool power_on);
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void dcn20_program_triple_buffer(
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const struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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bool enable_triple_buffer);
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void dcn20_enable_writeback(
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struct dc *dc,
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struct dc_writeback_info *wb_info,
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struct dc_state *context);
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void dcn20_disable_writeback(
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struct dc *dc,
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unsigned int dwb_pipe_inst);
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void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
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bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
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void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
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void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
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void dcn20_init_vm_ctx(
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struct dce_hwseq *hws,
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struct dc *dc,
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struct dc_virtual_addr_space_config *va_config,
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int vmid);
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void dcn20_set_flip_control_gsl(
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struct pipe_ctx *pipe_ctx,
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bool flip_immediate);
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void dcn20_dsc_pg_control(
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struct dce_hwseq *hws,
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unsigned int dsc_inst,
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bool power_on);
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void dcn20_fpga_init_hw(struct dc *dc);
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bool dcn20_wait_for_blank_complete(
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struct output_pixel_processor *opp);
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void dcn20_dccg_init(struct dce_hwseq *hws);
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int dcn20_init_sys_ctx(struct dce_hwseq *hws,
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struct dc *dc,
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struct dc_phy_addr_space_config *pa_config);
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#ifndef TRIM_FSFT
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bool dcn20_optimize_timing_for_fsft(struct dc *dc,
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struct dc_crtc_timing *timing,
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unsigned int max_input_rate_in_khz);
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#endif
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void dcn20_set_disp_pattern_generator(const struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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enum controller_dp_test_pattern test_pattern,
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enum controller_dp_color_space color_space,
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enum dc_color_depth color_depth,
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const struct tg_color *solid_color,
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int width, int height, int offset);
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void dcn20_update_visual_confirm_color(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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struct tg_color *color,
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int mpcc_id);
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#endif /* __DC_HWSS_DCN20_H__ */
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