126 lines
3.9 KiB
C
126 lines
3.9 KiB
C
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "dcn201_mpc.h"
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#define REG(reg)\
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mpc201->mpc_regs->reg
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#define CTX \
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mpc201->base.ctx
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#define DC_LOGGER \
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mpc201->base.ctx->logger
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#undef FN
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#define FN(reg_name, field_name) \
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mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
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static void mpc201_set_out_rate_control(
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struct mpc *mpc,
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int opp_id,
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bool enable,
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bool rate_2x_mode,
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struct mpc_dwb_flow_control *flow_control)
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{
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struct dcn201_mpc *mpc201 = TO_DCN201_MPC(mpc);
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REG_UPDATE_2(MUX[opp_id],
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MPC_OUT_RATE_CONTROL_DISABLE, !enable,
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MPC_OUT_RATE_CONTROL, rate_2x_mode);
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if (flow_control)
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REG_UPDATE_3(MUX[opp_id],
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MPC_OUT_FLOW_CONTROL_MODE, flow_control->flow_ctrl_mode,
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MPC_OUT_FLOW_CONTROL_COUNT0, flow_control->flow_ctrl_cnt0,
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MPC_OUT_FLOW_CONTROL_COUNT1, flow_control->flow_ctrl_cnt1);
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}
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static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
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{
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mpcc->mpcc_id = mpcc_inst;
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mpcc->dpp_id = 0xf;
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mpcc->mpcc_bot = NULL;
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mpcc->blnd_cfg.overlap_only = false;
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mpcc->blnd_cfg.global_alpha = 0xff;
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mpcc->blnd_cfg.global_gain = 0xff;
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mpcc->blnd_cfg.background_color_bpc = 4;
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mpcc->blnd_cfg.bottom_gain_mode = 0;
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mpcc->blnd_cfg.top_gain = 0x1f000;
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mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
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mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
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mpcc->sm_cfg.enable = false;
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mpcc->shared_bottom = false;
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}
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const struct mpc_funcs dcn201_mpc_funcs = {
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.read_mpcc_state = mpc1_read_mpcc_state,
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.insert_plane = mpc1_insert_plane,
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.remove_mpcc = mpc1_remove_mpcc,
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.mpc_init = mpc1_mpc_init,
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.mpc_init_single_inst = mpc1_mpc_init_single_inst,
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.update_blending = mpc2_update_blending,
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.cursor_lock = mpc1_cursor_lock,
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.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
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.get_mpcc_for_dpp_from_secondary = NULL,
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.wait_for_idle = mpc2_assert_idle_mpcc,
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.assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
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.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
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.set_denorm = mpc2_set_denorm,
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.set_denorm_clamp = mpc2_set_denorm_clamp,
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.set_output_csc = mpc2_set_output_csc,
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.set_ocsc_default = mpc2_set_ocsc_default,
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.set_output_gamma = mpc2_set_output_gamma,
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.set_out_rate_control = mpc201_set_out_rate_control,
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.power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
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.get_mpc_out_mux = mpc1_get_mpc_out_mux,
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.set_bg_color = mpc1_set_bg_color,
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};
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void dcn201_mpc_construct(struct dcn201_mpc *mpc201,
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struct dc_context *ctx,
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const struct dcn201_mpc_registers *mpc_regs,
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const struct dcn201_mpc_shift *mpc_shift,
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const struct dcn201_mpc_mask *mpc_mask,
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int num_mpcc)
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{
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int i;
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mpc201->base.ctx = ctx;
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mpc201->base.funcs = &dcn201_mpc_funcs;
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mpc201->mpc_regs = mpc_regs;
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mpc201->mpc_shift = mpc_shift;
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mpc201->mpc_mask = mpc_mask;
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mpc201->mpcc_in_use_mask = 0;
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mpc201->num_mpcc = num_mpcc;
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for (i = 0; i < MAX_MPCC; i++)
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mpc201_init_mpcc(&mpc201->base.mpcc_array[i], i);
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}
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