66 lines
2.5 KiB
C
66 lines
2.5 KiB
C
|
/*
|
||
|
|
* Copyright 2020 Advanced Micro Devices, Inc.
|
||
|
|
*
|
||
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||
|
|
* copy of this software and associated documentation files (the "Software"),
|
||
|
|
* to deal in the Software without restriction, including without limitation
|
||
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||
|
|
* Software is furnished to do so, subject to the following conditions:
|
||
|
|
*
|
||
|
|
* The above copyright notice and this permission notice shall be included in
|
||
|
|
* all copies or substantial portions of the Software.
|
||
|
|
*
|
||
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||
|
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||
|
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||
|
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||
|
|
*
|
||
|
|
* Authors: AMD
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifndef __DCN301_DCCG_H__
|
||
|
|
#define __DCN301_DCCG_H__
|
||
|
|
|
||
|
|
#include "dcn20/dcn20_dccg.h"
|
||
|
|
|
||
|
|
#define DCCG_REG_LIST_DCN301() \
|
||
|
|
SR(DPPCLK_DTO_CTRL),\
|
||
|
|
DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
|
||
|
|
DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
|
||
|
|
DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
|
||
|
|
DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
|
||
|
|
SR(REFCLK_CNTL)
|
||
|
|
|
||
|
|
#define DCCG_MASK_SH_LIST_DCN301(mask_sh) \
|
||
|
|
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
|
||
|
|
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
|
||
|
|
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
|
||
|
|
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
|
||
|
|
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
|
||
|
|
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
|
||
|
|
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
|
||
|
|
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
|
||
|
|
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
|
||
|
|
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
|
||
|
|
DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
|
||
|
|
DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
|
||
|
|
|
||
|
|
struct dccg *dccg301_create(
|
||
|
|
struct dc_context *ctx,
|
||
|
|
const struct dccg_registers *regs,
|
||
|
|
const struct dccg_shift *dccg_shift,
|
||
|
|
const struct dccg_mask *dccg_mask);
|
||
|
|
|
||
|
|
struct dccg *dccg301_create(
|
||
|
|
struct dc_context *ctx,
|
||
|
|
const struct dccg_registers *regs,
|
||
|
|
const struct dccg_shift *dccg_shift,
|
||
|
|
const struct dccg_mask *dccg_mask);
|
||
|
|
|
||
|
|
#endif //__DCN301_DCCG_H__
|