319 lines
9.2 KiB
C
319 lines
9.2 KiB
C
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DM_PP_SMU_IF__H
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#define DM_PP_SMU_IF__H
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/*
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* interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
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*/
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enum pp_smu_ver {
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/*
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* PP_SMU_INTERFACE_X should be interpreted as the interface defined
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* starting from X, where X is some family of ASICs. This is as
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* opposed to interfaces used only for X. There will be some degree
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* of interface sharing between families of ASIcs.
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*/
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PP_SMU_UNSUPPORTED,
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PP_SMU_VER_RV,
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PP_SMU_VER_NV,
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PP_SMU_VER_RN,
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PP_SMU_VER_MAX
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};
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struct pp_smu {
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enum pp_smu_ver ver;
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const void *pp;
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/*
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* interim extra handle for backwards compatibility
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* as some existing functionality not yet implemented
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* by ppsmu
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*/
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const void *dm;
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};
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enum pp_smu_status {
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PP_SMU_RESULT_UNDEFINED = 0,
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PP_SMU_RESULT_OK = 1,
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PP_SMU_RESULT_FAIL,
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PP_SMU_RESULT_UNSUPPORTED
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};
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#define PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN 0x0
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#define PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX 0xFFFF
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enum wm_type {
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WM_TYPE_PSTATE_CHG = 0,
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WM_TYPE_RETRAINING = 1,
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};
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/* This structure is a copy of WatermarkRowGeneric_t defined by smuxx_driver_if.h*/
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struct pp_smu_wm_set_range {
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uint16_t min_fill_clk_mhz;
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uint16_t max_fill_clk_mhz;
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uint16_t min_drain_clk_mhz;
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uint16_t max_drain_clk_mhz;
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uint8_t wm_inst;
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uint8_t wm_type;
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};
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#define MAX_WATERMARK_SETS 4
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struct pp_smu_wm_range_sets {
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unsigned int num_reader_wm_sets;
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struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS];
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unsigned int num_writer_wm_sets;
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struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS];
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};
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struct pp_smu_funcs_rv {
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struct pp_smu pp_smu;
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/* PPSMC_MSG_SetDisplayCount
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* 0 triggers S0i2 optimization
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*/
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void (*set_display_count)(struct pp_smu *pp, int count);
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/* reader and writer WM's are sent together as part of one table*/
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/*
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* PPSMC_MSG_SetDriverDramAddrHigh
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* PPSMC_MSG_SetDriverDramAddrLow
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* PPSMC_MSG_TransferTableDram2Smu
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*
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* */
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void (*set_wm_ranges)(struct pp_smu *pp,
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struct pp_smu_wm_range_sets *ranges);
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/* PPSMC_MSG_SetHardMinDcfclkByFreq
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* fixed clock at requested freq, either from FCH bypass or DFS
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*/
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void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
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/* PPSMC_MSG_SetMinDeepSleepDcfclk
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* when DF is in cstate, dcf clock is further divided down
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* to just above given frequency
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*/
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void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
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/* PPSMC_MSG_SetHardMinFclkByFreq
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* FCLK will vary with DPM, but never below requested hard min
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*/
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void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
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/* PPSMC_MSG_SetHardMinSocclkByFreq
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* Needed for DWB support
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*/
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void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
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/* PME w/a */
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void (*set_pme_wa_enable)(struct pp_smu *pp);
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};
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/* Used by pp_smu_funcs_nv.set_voltage_by_freq
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*
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*/
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enum pp_smu_nv_clock_id {
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PP_SMU_NV_DISPCLK,
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PP_SMU_NV_PHYCLK,
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PP_SMU_NV_PIXELCLK
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};
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/*
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* Used by pp_smu_funcs_nv.get_maximum_sustainable_clocks
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*/
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struct pp_smu_nv_clock_table {
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// voltage managed SMU, freq set by driver
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unsigned int displayClockInKhz;
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unsigned int dppClockInKhz;
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unsigned int phyClockInKhz;
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unsigned int pixelClockInKhz;
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unsigned int dscClockInKhz;
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// freq/voltage managed by SMU
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unsigned int fabricClockInKhz;
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unsigned int socClockInKhz;
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unsigned int dcfClockInKhz;
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unsigned int uClockInKhz;
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};
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struct pp_smu_funcs_nv {
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struct pp_smu pp_smu;
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/* PPSMC_MSG_SetDisplayCount
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* 0 triggers S0i2 optimization
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*/
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enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count);
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/* PPSMC_MSG_SetHardMinDcfclkByFreq
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* fixed clock at requested freq, either from FCH bypass or DFS
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*/
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enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz);
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/* PPSMC_MSG_SetMinDeepSleepDcfclk
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* when DF is in cstate, dcf clock is further divided down
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* to just above given frequency
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*/
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enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz);
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/* PPSMC_MSG_SetHardMinUclkByFreq
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* UCLK will vary with DPM, but never below requested hard min
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*/
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enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz);
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/* PPSMC_MSG_SetHardMinSocclkByFreq
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* Needed for DWB support
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*/
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enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz);
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/* PME w/a */
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enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);
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/* PPSMC_MSG_SetHardMinByFreq
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* Needed to set ASIC voltages for clocks programmed by DAL
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*/
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enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp,
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enum pp_smu_nv_clock_id clock_id, int Mhz);
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/* reader and writer WM's are sent together as part of one table*/
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/*
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* PPSMC_MSG_SetDriverDramAddrHigh
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* PPSMC_MSG_SetDriverDramAddrLow
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* PPSMC_MSG_TransferTableDram2Smu
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*
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* on DCN20:
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* reader fill clk = uclk
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* reader drain clk = dcfclk
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* writer fill clk = socclk
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* writer drain clk = uclk
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* */
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enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
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struct pp_smu_wm_range_sets *ranges);
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/* Not a single SMU message. This call should return maximum sustainable limit for all
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* clocks that DC depends on. These will be used as basis for mode enumeration.
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*/
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enum pp_smu_status (*get_maximum_sustainable_clocks)(struct pp_smu *pp,
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struct pp_smu_nv_clock_table *max_clocks);
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/* This call should return the discrete uclk DPM states available
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*/
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enum pp_smu_status (*get_uclk_dpm_states)(struct pp_smu *pp,
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unsigned int *clock_values_in_khz, unsigned int *num_states);
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/* Not a single SMU message. This call informs PPLIB that display will not be able
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* to perform pstate handshaking in its current state. Typically this handshake
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* is used to perform uCLK switching, so disabling pstate disables uCLK switching.
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*
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* Note that when setting handshake to unsupported, the call is pre-emptive. That means
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* DC will make the call BEFORE setting up the display state which would cause pstate
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* request to go un-acked. Only when the call completes should such a state be applied to
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* DC hardware
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*/
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enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp,
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bool pstate_handshake_supported);
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};
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#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
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#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
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#define PP_SMU_NUM_FCLK_DPM_LEVELS 4
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#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4
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#define PP_SMU_NUM_DCLK_DPM_LEVELS 8
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#define PP_SMU_NUM_VCLK_DPM_LEVELS 8
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struct dpm_clock {
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uint32_t Freq; // In MHz
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uint32_t Vol; // Millivolts with 2 fractional bits
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};
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/* this is a copy of the structure defined in smuxx_driver_if.h*/
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struct dpm_clocks {
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struct dpm_clock DcfClocks[PP_SMU_NUM_DCFCLK_DPM_LEVELS];
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struct dpm_clock SocClocks[PP_SMU_NUM_SOCCLK_DPM_LEVELS];
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struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS];
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struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS];
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struct dpm_clock VClocks[PP_SMU_NUM_VCLK_DPM_LEVELS];
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struct dpm_clock DClocks[PP_SMU_NUM_DCLK_DPM_LEVELS];
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};
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struct pp_smu_funcs_rn {
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struct pp_smu pp_smu;
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/*
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* reader and writer WM's are sent together as part of one table
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*
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* PPSMC_MSG_SetDriverDramAddrHigh
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* PPSMC_MSG_SetDriverDramAddrLow
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* PPSMC_MSG_TransferTableDram2Smu
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*
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*/
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enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
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struct pp_smu_wm_range_sets *ranges);
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enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
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struct dpm_clocks *clock_table);
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};
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struct pp_smu_funcs_vgh {
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struct pp_smu pp_smu;
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/*
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* reader and writer WM's are sent together as part of one table
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*
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* PPSMC_MSG_SetDriverDramAddrHigh
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* PPSMC_MSG_SetDriverDramAddrLow
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* PPSMC_MSG_TransferTableDram2Smu
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*
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*/
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// TODO: Check whether this is moved to DAL, and remove as needed
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enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
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struct pp_smu_wm_range_sets *ranges);
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// TODO: Check whether this is moved to DAL, and remove as needed
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enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
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struct dpm_clocks *clock_table);
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enum pp_smu_status (*notify_smu_timeout) (struct pp_smu *pp);
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};
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struct pp_smu_funcs {
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struct pp_smu ctx;
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union {
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struct pp_smu_funcs_rv rv_funcs;
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struct pp_smu_funcs_nv nv_funcs;
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struct pp_smu_funcs_rn rn_funcs;
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struct pp_smu_funcs_vgh vgh_funcs;
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};
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};
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#endif /* DM_PP_SMU_IF__H */
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