398 lines
14 KiB
C
398 lines
14 KiB
C
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "vega12/smu9_driver_if.h"
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#include "vega12_processpptables.h"
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#include "ppatomfwctrl.h"
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#include "atomfirmware.h"
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#include "pp_debug.h"
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#include "cgs_common.h"
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#include "vega12_pptable.h"
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static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
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enum phm_platform_caps cap)
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{
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if (enable)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
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else
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
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}
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static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
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{
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int index = GetIndexIntoMasterDataTable(powerplayinfo);
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u16 size;
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u8 frev, crev;
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const void *table_address = hwmgr->soft_pp_table;
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if (!table_address) {
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table_address = (ATOM_Vega12_POWERPLAYTABLE *)
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smu_atom_get_data_table(hwmgr->adev, index,
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&size, &frev, &crev);
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hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
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hwmgr->soft_pp_table_size = size;
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}
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return table_address;
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}
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static int check_powerplay_tables(
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struct pp_hwmgr *hwmgr,
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const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
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{
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PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
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ATOM_VEGA12_TABLE_REVISION_VEGA12),
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"Unsupported PPTable format!", return -1);
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PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
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"Invalid PowerPlay Table!", return -1);
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return 0;
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}
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static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
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{
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set_hw_cap(
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hwmgr,
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0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY),
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PHM_PlatformCaps_PowerPlaySupport);
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set_hw_cap(
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hwmgr,
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0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
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PHM_PlatformCaps_BiosPowerSourceControl);
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set_hw_cap(
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hwmgr,
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0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BACO),
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PHM_PlatformCaps_BACO);
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set_hw_cap(
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hwmgr,
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0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO),
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PHM_PlatformCaps_BAMACO);
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return 0;
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}
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static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
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{
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struct pp_atomfwctrl_smc_dpm_parameters smc_dpm_table;
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PP_ASSERT_WITH_CODE(
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pp_atomfwctrl_get_smc_dpm_information(hwmgr, &smc_dpm_table) == 0,
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"[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
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return -1);
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ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table.liquid1_i2c_address;
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ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table.liquid2_i2c_address;
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ppsmc_pptable->Vr_I2C_address = smc_dpm_table.vr_i2c_address;
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ppsmc_pptable->Plx_I2C_address = smc_dpm_table.plx_i2c_address;
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ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table.liquid_i2c_linescl;
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ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table.liquid_i2c_linesda;
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ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table.vr_i2c_linescl;
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ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table.vr_i2c_linesda;
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ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table.plx_i2c_linescl;
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ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table.plx_i2c_linesda;
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ppsmc_pptable->VrSensorPresent = smc_dpm_table.vrsensorpresent;
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ppsmc_pptable->LiquidSensorPresent = smc_dpm_table.liquidsensorpresent;
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ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table.maxvoltagestepgfx;
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ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table.maxvoltagestepsoc;
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ppsmc_pptable->VddGfxVrMapping = smc_dpm_table.vddgfxvrmapping;
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ppsmc_pptable->VddSocVrMapping = smc_dpm_table.vddsocvrmapping;
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ppsmc_pptable->VddMem0VrMapping = smc_dpm_table.vddmem0vrmapping;
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ppsmc_pptable->VddMem1VrMapping = smc_dpm_table.vddmem1vrmapping;
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ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table.gfxulvphasesheddingmask;
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ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table.soculvphasesheddingmask;
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ppsmc_pptable->GfxMaxCurrent = smc_dpm_table.gfxmaxcurrent;
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ppsmc_pptable->GfxOffset = smc_dpm_table.gfxoffset;
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ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table.padding_telemetrygfx;
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ppsmc_pptable->SocMaxCurrent = smc_dpm_table.socmaxcurrent;
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ppsmc_pptable->SocOffset = smc_dpm_table.socoffset;
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ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table.padding_telemetrysoc;
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ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table.mem0maxcurrent;
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ppsmc_pptable->Mem0Offset = smc_dpm_table.mem0offset;
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ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table.padding_telemetrymem0;
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ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table.mem1maxcurrent;
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ppsmc_pptable->Mem1Offset = smc_dpm_table.mem1offset;
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ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table.padding_telemetrymem1;
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ppsmc_pptable->AcDcGpio = smc_dpm_table.acdcgpio;
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ppsmc_pptable->AcDcPolarity = smc_dpm_table.acdcpolarity;
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ppsmc_pptable->VR0HotGpio = smc_dpm_table.vr0hotgpio;
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ppsmc_pptable->VR0HotPolarity = smc_dpm_table.vr0hotpolarity;
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ppsmc_pptable->VR1HotGpio = smc_dpm_table.vr1hotgpio;
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ppsmc_pptable->VR1HotPolarity = smc_dpm_table.vr1hotpolarity;
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ppsmc_pptable->Padding1 = smc_dpm_table.padding1;
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ppsmc_pptable->Padding2 = smc_dpm_table.padding2;
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ppsmc_pptable->LedPin0 = smc_dpm_table.ledpin0;
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ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1;
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ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2;
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ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table.pllgfxclkspreadenabled;
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ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table.pllgfxclkspreadpercent;
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ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table.pllgfxclkspreadfreq;
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ppsmc_pptable->UclkSpreadEnabled = 0;
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ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent;
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ppsmc_pptable->UclkSpreadFreq = smc_dpm_table.uclkspreadfreq;
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ppsmc_pptable->SocclkSpreadEnabled = 0;
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ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent;
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ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq;
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ppsmc_pptable->AcgGfxclkSpreadEnabled = smc_dpm_table.acggfxclkspreadenabled;
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ppsmc_pptable->AcgGfxclkSpreadPercent = smc_dpm_table.acggfxclkspreadpercent;
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ppsmc_pptable->AcgGfxclkSpreadFreq = smc_dpm_table.acggfxclkspreadfreq;
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ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
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ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
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return 0;
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}
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#define VEGA12_ENGINECLOCK_HARDMAX 198000
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static int init_powerplay_table_information(
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struct pp_hwmgr *hwmgr,
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const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
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{
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struct phm_ppt_v3_information *pptable_information =
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(struct phm_ppt_v3_information *)hwmgr->pptable;
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uint32_t disable_power_control = 0;
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hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType;
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pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType;
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set_hw_cap(hwmgr,
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ATOM_VEGA12_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
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PHM_PlatformCaps_ThermalController);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
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if (le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]) > VEGA12_ENGINECLOCK_HARDMAX)
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hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX;
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else
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hwmgr->platform_descriptor.overdriveLimit.engineClock =
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le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]);
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hwmgr->platform_descriptor.overdriveLimit.memoryClock =
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le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX]);
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phm_copy_overdrive_settings_limits_array(hwmgr,
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&pptable_information->od_settings_max,
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powerplay_table->ODSettingsMax,
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ATOM_VEGA12_ODSETTING_COUNT);
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phm_copy_overdrive_settings_limits_array(hwmgr,
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&pptable_information->od_settings_min,
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powerplay_table->ODSettingsMin,
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ATOM_VEGA12_ODSETTING_COUNT);
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/* hwmgr->platformDescriptor.minOverdriveVDDC = 0;
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hwmgr->platformDescriptor.maxOverdriveVDDC = 0;
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hwmgr->platformDescriptor.overdriveVDDCStep = 0; */
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if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
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&& hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport);
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pptable_information->us_small_power_limit1 = le16_to_cpu(powerplay_table->usSmallPowerLimit1);
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pptable_information->us_small_power_limit2 = le16_to_cpu(powerplay_table->usSmallPowerLimit2);
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pptable_information->us_boost_power_limit = le16_to_cpu(powerplay_table->usBoostPowerLimit);
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pptable_information->us_od_turbo_power_limit = le16_to_cpu(powerplay_table->usODTurboPowerLimit);
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pptable_information->us_od_powersave_power_limit = le16_to_cpu(powerplay_table->usODPowerSavePowerLimit);
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pptable_information->us_software_shutdown_temp = le16_to_cpu(powerplay_table->usSoftwareShutdownTemp);
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hwmgr->platform_descriptor.TDPODLimit = le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE]);
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disable_power_control = 0;
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if (!disable_power_control) {
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/* enable TDP overdrive (PowerControl) feature as well if supported */
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if (hwmgr->platform_descriptor.TDPODLimit)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_PowerControl);
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}
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phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockMax, ATOM_VEGA12_PPCLOCK_COUNT);
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phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockMin, ATOM_VEGA12_PPCLOCK_COUNT);
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pptable_information->smc_pptable = kmemdup(&(powerplay_table->smcPPTable),
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sizeof(PPTable_t), GFP_KERNEL);
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if (pptable_information->smc_pptable == NULL)
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return -ENOMEM;
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return append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
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}
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static int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
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{
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int result = 0;
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const ATOM_Vega12_POWERPLAYTABLE *powerplay_table;
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hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
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PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
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"Failed to allocate hwmgr->pptable!", return -ENOMEM);
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powerplay_table = get_powerplay_table(hwmgr);
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PP_ASSERT_WITH_CODE((powerplay_table != NULL),
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"Missing PowerPlay Table!", return -1);
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result = check_powerplay_tables(hwmgr, powerplay_table);
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PP_ASSERT_WITH_CODE((result == 0),
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"check_powerplay_tables failed", return result);
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result = set_platform_caps(hwmgr,
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le32_to_cpu(powerplay_table->ulPlatformCaps));
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PP_ASSERT_WITH_CODE((result == 0),
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"set_platform_caps failed", return result);
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result = init_powerplay_table_information(hwmgr, powerplay_table);
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PP_ASSERT_WITH_CODE((result == 0),
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"init_powerplay_table_information failed", return result);
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return result;
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}
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static int vega12_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
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{
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struct phm_ppt_v3_information *pp_table_info =
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(struct phm_ppt_v3_information *)(hwmgr->pptable);
|
||
|
|
|
||
|
|
kfree(pp_table_info->power_saving_clock_max);
|
||
|
|
pp_table_info->power_saving_clock_max = NULL;
|
||
|
|
|
||
|
|
kfree(pp_table_info->power_saving_clock_min);
|
||
|
|
pp_table_info->power_saving_clock_min = NULL;
|
||
|
|
|
||
|
|
kfree(pp_table_info->od_settings_max);
|
||
|
|
pp_table_info->od_settings_max = NULL;
|
||
|
|
|
||
|
|
kfree(pp_table_info->od_settings_min);
|
||
|
|
pp_table_info->od_settings_min = NULL;
|
||
|
|
|
||
|
|
kfree(pp_table_info->smc_pptable);
|
||
|
|
pp_table_info->smc_pptable = NULL;
|
||
|
|
|
||
|
|
kfree(hwmgr->pptable);
|
||
|
|
hwmgr->pptable = NULL;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct pp_table_func vega12_pptable_funcs = {
|
||
|
|
.pptable_init = vega12_pp_tables_initialize,
|
||
|
|
.pptable_fini = vega12_pp_tables_uninitialize,
|
||
|
|
};
|
||
|
|
|
||
|
|
#if 0
|
||
|
|
static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
|
||
|
|
uint16_t classification, uint16_t classification2)
|
||
|
|
{
|
||
|
|
uint32_t result = 0;
|
||
|
|
|
||
|
|
if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
|
||
|
|
result |= PP_StateClassificationFlag_Boot;
|
||
|
|
|
||
|
|
if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
|
||
|
|
result |= PP_StateClassificationFlag_Thermal;
|
||
|
|
|
||
|
|
if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
|
||
|
|
result |= PP_StateClassificationFlag_LimitedPowerSource;
|
||
|
|
|
||
|
|
if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
|
||
|
|
result |= PP_StateClassificationFlag_Rest;
|
||
|
|
|
||
|
|
if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
|
||
|
|
result |= PP_StateClassificationFlag_Forced;
|
||
|
|
|
||
|
|
if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
|
||
|
|
result |= PP_StateClassificationFlag_ACPI;
|
||
|
|
|
||
|
|
if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
|
||
|
|
result |= PP_StateClassificationFlag_LimitedPowerSource_2;
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
int vega12_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
|
||
|
|
uint32_t entry_index, struct pp_power_state *power_state,
|
||
|
|
int (*call_back_func)(struct pp_hwmgr *, void *,
|
||
|
|
struct pp_power_state *, void *, uint32_t))
|
||
|
|
{
|
||
|
|
int result = 0;
|
||
|
|
const ATOM_Vega12_State_Array *state_arrays;
|
||
|
|
const ATOM_Vega12_State *state_entry;
|
||
|
|
const ATOM_Vega12_POWERPLAYTABLE *pp_table =
|
||
|
|
get_powerplay_table(hwmgr);
|
||
|
|
|
||
|
|
PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
|
||
|
|
return -1;);
|
||
|
|
power_state->classification.bios_index = entry_index;
|
||
|
|
|
||
|
|
if (pp_table->sHeader.format_revision >=
|
||
|
|
ATOM_Vega12_TABLE_REVISION_VEGA12) {
|
||
|
|
state_arrays = (ATOM_Vega12_State_Array *)
|
||
|
|
(((unsigned long)pp_table) +
|
||
|
|
le16_to_cpu(pp_table->usStateArrayOffset));
|
||
|
|
|
||
|
|
PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
|
||
|
|
"Invalid PowerPlay Table State Array Offset.",
|
||
|
|
return -1);
|
||
|
|
PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
|
||
|
|
"Invalid PowerPlay Table State Array.",
|
||
|
|
return -1);
|
||
|
|
PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
|
||
|
|
"Invalid PowerPlay Table State Array Entry.",
|
||
|
|
return -1);
|
||
|
|
|
||
|
|
state_entry = &(state_arrays->states[entry_index]);
|
||
|
|
|
||
|
|
result = call_back_func(hwmgr, (void *)state_entry, power_state,
|
||
|
|
(void *)pp_table,
|
||
|
|
make_classification_flags(hwmgr,
|
||
|
|
le16_to_cpu(state_entry->usClassification),
|
||
|
|
le16_to_cpu(state_entry->usClassification2)));
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!result && (power_state->classification.flags &
|
||
|
|
PP_StateClassificationFlag_Boot))
|
||
|
|
result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
#endif
|