632 lines
18 KiB
C
632 lines
18 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU71_DISCRETE_H
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#define SMU71_DISCRETE_H
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#include "smu71.h"
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#if !defined(SMC_MICROCODE)
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#pragma pack(push, 1)
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#endif
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#define VDDC_ON_SVI2 0x1
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#define VDDCI_ON_SVI2 0x2
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#define MVDD_ON_SVI2 0x4
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struct SMU71_Discrete_VoltageLevel
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{
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uint16_t Voltage;
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uint16_t StdVoltageHiSidd;
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uint16_t StdVoltageLoSidd;
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uint8_t Smio;
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uint8_t padding;
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};
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typedef struct SMU71_Discrete_VoltageLevel SMU71_Discrete_VoltageLevel;
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struct SMU71_Discrete_GraphicsLevel
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{
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uint32_t MinVddc;
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uint32_t MinVddcPhases;
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uint32_t SclkFrequency;
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uint8_t pcieDpmLevel;
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uint8_t DeepSleepDivId;
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uint16_t ActivityLevel;
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uint32_t CgSpllFuncCntl3;
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uint32_t CgSpllFuncCntl4;
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uint32_t SpllSpreadSpectrum;
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uint32_t SpllSpreadSpectrum2;
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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uint8_t SclkDid;
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uint8_t DisplayWatermark;
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uint8_t EnabledForActivity;
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uint8_t EnabledForThrottle;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t PowerThrottle;
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};
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typedef struct SMU71_Discrete_GraphicsLevel SMU71_Discrete_GraphicsLevel;
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struct SMU71_Discrete_ACPILevel
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{
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uint32_t Flags;
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uint32_t MinVddc;
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uint32_t MinVddcPhases;
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uint32_t SclkFrequency;
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uint8_t SclkDid;
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uint8_t DisplayWatermark;
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uint8_t DeepSleepDivId;
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uint8_t padding;
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uint32_t CgSpllFuncCntl;
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uint32_t CgSpllFuncCntl2;
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uint32_t CgSpllFuncCntl3;
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uint32_t CgSpllFuncCntl4;
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uint32_t SpllSpreadSpectrum;
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uint32_t SpllSpreadSpectrum2;
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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};
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typedef struct SMU71_Discrete_ACPILevel SMU71_Discrete_ACPILevel;
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struct SMU71_Discrete_Ulv
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{
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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uint16_t VddcOffset;
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uint8_t VddcOffsetVid;
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uint8_t VddcPhase;
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uint32_t Reserved;
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};
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typedef struct SMU71_Discrete_Ulv SMU71_Discrete_Ulv;
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struct SMU71_Discrete_MemoryLevel
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{
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uint32_t MinVddc;
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uint32_t MinVddcPhases;
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uint32_t MinVddci;
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uint32_t MinMvdd;
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uint32_t MclkFrequency;
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uint8_t EdcReadEnable;
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uint8_t EdcWriteEnable;
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uint8_t RttEnable;
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uint8_t StutterEnable;
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uint8_t StrobeEnable;
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uint8_t StrobeRatio;
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uint8_t EnabledForThrottle;
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uint8_t EnabledForActivity;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t padding;
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uint16_t ActivityLevel;
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uint8_t DisplayWatermark;
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uint8_t padding1;
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uint32_t MpllFuncCntl;
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uint32_t MpllFuncCntl_1;
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uint32_t MpllFuncCntl_2;
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uint32_t MpllAdFuncCntl;
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uint32_t MpllDqFuncCntl;
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uint32_t MclkPwrmgtCntl;
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uint32_t DllCntl;
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uint32_t MpllSs1;
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uint32_t MpllSs2;
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};
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typedef struct SMU71_Discrete_MemoryLevel SMU71_Discrete_MemoryLevel;
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struct SMU71_Discrete_LinkLevel
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{
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uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
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uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
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uint8_t EnabledForActivity;
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uint8_t SPC;
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uint32_t DownThreshold;
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uint32_t UpThreshold;
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uint32_t Reserved;
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};
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typedef struct SMU71_Discrete_LinkLevel SMU71_Discrete_LinkLevel;
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#ifdef SMU__DYNAMIC_MCARB_SETTINGS
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// MC ARB DRAM Timing registers.
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struct SMU71_Discrete_MCArbDramTimingTableEntry
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{
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uint32_t McArbDramTiming;
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uint32_t McArbDramTiming2;
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uint8_t McArbBurstTime;
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uint8_t padding[3];
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};
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typedef struct SMU71_Discrete_MCArbDramTimingTableEntry SMU71_Discrete_MCArbDramTimingTableEntry;
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struct SMU71_Discrete_MCArbDramTimingTable
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{
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SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
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};
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typedef struct SMU71_Discrete_MCArbDramTimingTable SMU71_Discrete_MCArbDramTimingTable;
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#endif
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// UVD VCLK/DCLK state (level) definition.
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struct SMU71_Discrete_UvdLevel
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{
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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uint16_t MinVddc;
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uint8_t MinVddcPhases;
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uint8_t VclkDivider;
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uint8_t DclkDivider;
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uint8_t padding[3];
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};
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typedef struct SMU71_Discrete_UvdLevel SMU71_Discrete_UvdLevel;
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// Clocks for other external blocks (VCE, ACP, SAMU).
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struct SMU71_Discrete_ExtClkLevel
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{
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uint32_t Frequency;
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uint16_t MinVoltage;
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uint8_t MinPhases;
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uint8_t Divider;
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};
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typedef struct SMU71_Discrete_ExtClkLevel SMU71_Discrete_ExtClkLevel;
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// Everything that we need to keep track of about the current state.
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// Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters
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// that need to be checked later.
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// We don't need to cache everything about a state, just a few parameters.
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struct SMU71_Discrete_StateInfo
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{
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uint32_t SclkFrequency;
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uint32_t MclkFrequency;
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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uint32_t SamclkFrequency;
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uint32_t AclkFrequency;
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uint32_t EclkFrequency;
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uint16_t MvddVoltage;
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uint16_t padding16;
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uint8_t DisplayWatermark;
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uint8_t McArbIndex;
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uint8_t McRegIndex;
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uint8_t SeqIndex;
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uint8_t SclkDid;
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int8_t SclkIndex;
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int8_t MclkIndex;
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uint8_t PCIeGen;
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};
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typedef struct SMU71_Discrete_StateInfo SMU71_Discrete_StateInfo;
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struct SMU71_Discrete_DpmTable
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{
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// Multi-DPM controller settings
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SMU71_PIDController GraphicsPIDController;
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SMU71_PIDController MemoryPIDController;
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SMU71_PIDController LinkPIDController;
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uint32_t SystemFlags;
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// SMIO masks for voltage and phase controls
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uint32_t SmioMaskVddcVid;
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uint32_t SmioMaskVddcPhase;
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uint32_t SmioMaskVddciVid;
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uint32_t SmioMaskMvddVid;
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uint32_t VddcLevelCount;
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uint32_t VddciLevelCount;
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uint32_t MvddLevelCount;
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SMU71_Discrete_VoltageLevel VddcLevel [SMU71_MAX_LEVELS_VDDC];
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SMU71_Discrete_VoltageLevel VddciLevel [SMU71_MAX_LEVELS_VDDCI];
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SMU71_Discrete_VoltageLevel MvddLevel [SMU71_MAX_LEVELS_MVDD];
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uint8_t GraphicsDpmLevelCount;
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uint8_t MemoryDpmLevelCount;
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uint8_t LinkLevelCount;
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uint8_t MasterDeepSleepControl;
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uint32_t Reserved[5];
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// State table entries for each DPM state
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SMU71_Discrete_GraphicsLevel GraphicsLevel [SMU71_MAX_LEVELS_GRAPHICS];
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SMU71_Discrete_MemoryLevel MemoryACPILevel;
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SMU71_Discrete_MemoryLevel MemoryLevel [SMU71_MAX_LEVELS_MEMORY];
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SMU71_Discrete_LinkLevel LinkLevel [SMU71_MAX_LEVELS_LINK];
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SMU71_Discrete_ACPILevel ACPILevel;
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uint32_t SclkStepSize;
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uint32_t Smio [SMU71_MAX_ENTRIES_SMIO];
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uint8_t GraphicsBootLevel;
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uint8_t GraphicsVoltageChangeEnable;
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uint8_t GraphicsThermThrottleEnable;
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uint8_t GraphicsInterval;
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uint8_t VoltageInterval;
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uint8_t ThermalInterval;
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uint16_t TemperatureLimitHigh;
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uint16_t TemperatureLimitLow;
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uint8_t MemoryBootLevel;
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uint8_t MemoryVoltageChangeEnable;
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uint8_t MemoryInterval;
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uint8_t MemoryThermThrottleEnable;
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uint8_t MergedVddci;
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uint8_t padding2;
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uint16_t VoltageResponseTime;
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uint16_t PhaseResponseTime;
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uint8_t PCIeBootLinkLevel;
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uint8_t PCIeGenInterval;
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uint8_t DTEInterval;
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uint8_t DTEMode;
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uint8_t SVI2Enable;
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uint8_t VRHotGpio;
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uint8_t AcDcGpio;
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uint8_t ThermGpio;
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uint32_t DisplayCac;
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uint16_t MaxPwr;
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uint16_t NomPwr;
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uint16_t FpsHighThreshold;
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uint16_t FpsLowThreshold;
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uint16_t BAPMTI_R [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
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uint16_t BAPMTI_RC [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
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uint8_t DTEAmbientTempBase;
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uint8_t DTETjOffset;
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uint8_t GpuTjMax;
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uint8_t GpuTjHyst;
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uint16_t BootVddc;
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uint16_t BootVddci;
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uint16_t BootMVdd;
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uint16_t padding;
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uint32_t BAPM_TEMP_GRADIENT;
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uint32_t LowSclkInterruptThreshold;
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uint32_t VddGfxReChkWait;
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uint16_t PPM_PkgPwrLimit;
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uint16_t PPM_TemperatureLimit;
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uint16_t DefaultTdp;
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uint16_t TargetTdp;
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};
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typedef struct SMU71_Discrete_DpmTable SMU71_Discrete_DpmTable;
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// --------------------------------------------------- AC Timing Parameters ------------------------------------------------
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#define SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
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#define SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU71_MAX_LEVELS_MEMORY
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struct SMU71_Discrete_MCRegisterAddress
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{
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uint16_t s0;
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uint16_t s1;
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};
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typedef struct SMU71_Discrete_MCRegisterAddress SMU71_Discrete_MCRegisterAddress;
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struct SMU71_Discrete_MCRegisterSet
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{
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uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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};
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typedef struct SMU71_Discrete_MCRegisterSet SMU71_Discrete_MCRegisterSet;
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struct SMU71_Discrete_MCRegisters
|
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{
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uint8_t last;
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uint8_t reserved[3];
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SMU71_Discrete_MCRegisterAddress address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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SMU71_Discrete_MCRegisterSet data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
|
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};
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typedef struct SMU71_Discrete_MCRegisters SMU71_Discrete_MCRegisters;
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// --------------------------------------------------- Fan Table -----------------------------------------------------------
|
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struct SMU71_Discrete_FanTable
|
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{
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uint16_t FdoMode;
|
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int16_t TempMin;
|
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int16_t TempMed;
|
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int16_t TempMax;
|
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int16_t Slope1;
|
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int16_t Slope2;
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int16_t FdoMin;
|
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int16_t HystUp;
|
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int16_t HystDown;
|
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int16_t HystSlope;
|
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int16_t TempRespLim;
|
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int16_t TempCurr;
|
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int16_t SlopeCurr;
|
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int16_t PwmCurr;
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uint32_t RefreshPeriod;
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int16_t FdoMax;
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uint8_t TempSrc;
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int8_t Padding;
|
||
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};
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typedef struct SMU71_Discrete_FanTable SMU71_Discrete_FanTable;
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#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
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#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
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struct SMU71_MclkDpmScoreboard
|
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|
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{
|
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|
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uint32_t PercentageBusy;
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int32_t PIDError;
|
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int32_t PIDIntegral;
|
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int32_t PIDOutput;
|
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|
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|
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uint32_t SigmaDeltaAccum;
|
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|
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uint32_t SigmaDeltaOutput;
|
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|
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uint32_t SigmaDeltaLevel;
|
||
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|
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|
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uint32_t UtilizationSetpoint;
|
||
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|
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|
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uint8_t TdpClampMode;
|
||
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uint8_t TdcClampMode;
|
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uint8_t ThermClampMode;
|
||
|
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uint8_t VoltageBusy;
|
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|
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|
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int8_t CurrLevel;
|
||
|
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int8_t TargLevel;
|
||
|
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uint8_t LevelChangeInProgress;
|
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uint8_t UpHyst;
|
||
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|
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uint8_t DownHyst;
|
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uint8_t VoltageDownHyst;
|
||
|
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uint8_t DpmEnable;
|
||
|
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uint8_t DpmRunning;
|
||
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|
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|
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uint8_t DpmForce;
|
||
|
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uint8_t DpmForceLevel;
|
||
|
|
uint8_t DisplayWatermark;
|
||
|
|
uint8_t McArbIndex;
|
||
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|
||
|
|
uint32_t MinimumPerfMclk;
|
||
|
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|
||
|
|
uint8_t AcpiReq;
|
||
|
|
uint8_t AcpiAck;
|
||
|
|
uint8_t MclkSwitchInProgress;
|
||
|
|
uint8_t MclkSwitchCritical;
|
||
|
|
|
||
|
|
uint8_t TargetMclkIndex;
|
||
|
|
uint8_t TargetMvddIndex;
|
||
|
|
uint8_t MclkSwitchResult;
|
||
|
|
|
||
|
|
uint8_t EnabledLevelsChange;
|
||
|
|
|
||
|
|
uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_MEMORY];
|
||
|
|
uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_MEMORY];
|
||
|
|
|
||
|
|
void (*TargetStateCalculator)(uint8_t);
|
||
|
|
void (*SavedTargetStateCalculator)(uint8_t);
|
||
|
|
|
||
|
|
uint16_t AutoDpmInterval;
|
||
|
|
uint16_t AutoDpmRange;
|
||
|
|
|
||
|
|
uint16_t MclkSwitchingTime;
|
||
|
|
uint8_t padding[2];
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_MclkDpmScoreboard SMU71_MclkDpmScoreboard;
|
||
|
|
|
||
|
|
struct SMU71_UlvScoreboard
|
||
|
|
{
|
||
|
|
uint8_t EnterUlv;
|
||
|
|
uint8_t ExitUlv;
|
||
|
|
uint8_t UlvActive;
|
||
|
|
uint8_t WaitingForUlv;
|
||
|
|
uint8_t UlvEnable;
|
||
|
|
uint8_t UlvRunning;
|
||
|
|
uint8_t UlvMasterEnable;
|
||
|
|
uint8_t padding;
|
||
|
|
uint32_t UlvAbortedCount;
|
||
|
|
uint32_t UlvTimeStamp;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_UlvScoreboard SMU71_UlvScoreboard;
|
||
|
|
|
||
|
|
struct SMU71_VddGfxScoreboard
|
||
|
|
{
|
||
|
|
uint8_t VddGfxEnable;
|
||
|
|
uint8_t VddGfxActive;
|
||
|
|
uint8_t padding[2];
|
||
|
|
|
||
|
|
uint32_t VddGfxEnteredCount;
|
||
|
|
uint32_t VddGfxAbortedCount;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_VddGfxScoreboard SMU71_VddGfxScoreboard;
|
||
|
|
|
||
|
|
struct SMU71_AcpiScoreboard {
|
||
|
|
uint32_t SavedInterruptMask[2];
|
||
|
|
uint8_t LastACPIRequest;
|
||
|
|
uint8_t CgBifResp;
|
||
|
|
uint8_t RequestType;
|
||
|
|
uint8_t Padding;
|
||
|
|
SMU71_Discrete_ACPILevel D0Level;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_AcpiScoreboard SMU71_AcpiScoreboard;
|
||
|
|
|
||
|
|
|
||
|
|
struct SMU71_Discrete_PmFuses {
|
||
|
|
// dw0-dw1
|
||
|
|
uint8_t BapmVddCVidHiSidd[8];
|
||
|
|
|
||
|
|
// dw2-dw3
|
||
|
|
uint8_t BapmVddCVidLoSidd[8];
|
||
|
|
|
||
|
|
// dw4-dw5
|
||
|
|
uint8_t VddCVid[8];
|
||
|
|
|
||
|
|
// dw6
|
||
|
|
uint8_t SviLoadLineEn;
|
||
|
|
uint8_t SviLoadLineVddC;
|
||
|
|
uint8_t SviLoadLineTrimVddC;
|
||
|
|
uint8_t SviLoadLineOffsetVddC;
|
||
|
|
|
||
|
|
// dw7
|
||
|
|
uint16_t TDC_VDDC_PkgLimit;
|
||
|
|
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
|
||
|
|
uint8_t TDC_MAWt;
|
||
|
|
|
||
|
|
// dw8
|
||
|
|
uint8_t TdcWaterfallCtl;
|
||
|
|
uint8_t LPMLTemperatureMin;
|
||
|
|
uint8_t LPMLTemperatureMax;
|
||
|
|
uint8_t Reserved;
|
||
|
|
|
||
|
|
// dw9-dw12
|
||
|
|
uint8_t LPMLTemperatureScaler[16];
|
||
|
|
|
||
|
|
// dw13-dw14
|
||
|
|
int16_t FuzzyFan_ErrorSetDelta;
|
||
|
|
int16_t FuzzyFan_ErrorRateSetDelta;
|
||
|
|
int16_t FuzzyFan_PwmSetDelta;
|
||
|
|
uint16_t Reserved6;
|
||
|
|
|
||
|
|
// dw15
|
||
|
|
uint8_t GnbLPML[16];
|
||
|
|
|
||
|
|
// dw15
|
||
|
|
uint8_t GnbLPMLMaxVid;
|
||
|
|
uint8_t GnbLPMLMinVid;
|
||
|
|
uint8_t Reserved1[2];
|
||
|
|
|
||
|
|
// dw16
|
||
|
|
uint16_t BapmVddCBaseLeakageHiSidd;
|
||
|
|
uint16_t BapmVddCBaseLeakageLoSidd;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_Discrete_PmFuses SMU71_Discrete_PmFuses;
|
||
|
|
|
||
|
|
struct SMU71_Discrete_Log_Header_Table {
|
||
|
|
uint32_t version;
|
||
|
|
uint32_t asic_id;
|
||
|
|
uint16_t flags;
|
||
|
|
uint16_t entry_size;
|
||
|
|
uint32_t total_size;
|
||
|
|
uint32_t num_of_entries;
|
||
|
|
uint8_t type;
|
||
|
|
uint8_t mode;
|
||
|
|
uint8_t filler_0[2];
|
||
|
|
uint32_t filler_1[2];
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_Discrete_Log_Header_Table SMU71_Discrete_Log_Header_Table;
|
||
|
|
|
||
|
|
struct SMU71_Discrete_Log_Cntl {
|
||
|
|
uint8_t Enabled;
|
||
|
|
uint8_t Type;
|
||
|
|
uint8_t padding[2];
|
||
|
|
uint32_t BufferSize;
|
||
|
|
uint32_t SamplesLogged;
|
||
|
|
uint32_t SampleSize;
|
||
|
|
uint32_t AddrL;
|
||
|
|
uint32_t AddrH;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_Discrete_Log_Cntl SMU71_Discrete_Log_Cntl;
|
||
|
|
|
||
|
|
#if defined SMU__DGPU_ONLY
|
||
|
|
#define CAC_ACC_NW_NUM_OF_SIGNALS 83
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
struct SMU71_Discrete_Cac_Collection_Table {
|
||
|
|
uint32_t temperature;
|
||
|
|
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
|
||
|
|
uint32_t filler[4];
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_Discrete_Cac_Collection_Table SMU71_Discrete_Cac_Collection_Table;
|
||
|
|
|
||
|
|
struct SMU71_Discrete_Cac_Verification_Table {
|
||
|
|
uint32_t VddcTotalPower;
|
||
|
|
uint32_t VddcLeakagePower;
|
||
|
|
uint32_t VddcConstantPower;
|
||
|
|
uint32_t VddcGfxDynamicPower;
|
||
|
|
uint32_t VddcUvdDynamicPower;
|
||
|
|
uint32_t VddcVceDynamicPower;
|
||
|
|
uint32_t VddcAcpDynamicPower;
|
||
|
|
uint32_t VddcPcieDynamicPower;
|
||
|
|
uint32_t VddcDceDynamicPower;
|
||
|
|
uint32_t VddcCurrent;
|
||
|
|
uint32_t VddcVoltage;
|
||
|
|
uint32_t VddciTotalPower;
|
||
|
|
uint32_t VddciLeakagePower;
|
||
|
|
uint32_t VddciConstantPower;
|
||
|
|
uint32_t VddciDynamicPower;
|
||
|
|
uint32_t Vddr1TotalPower;
|
||
|
|
uint32_t Vddr1LeakagePower;
|
||
|
|
uint32_t Vddr1ConstantPower;
|
||
|
|
uint32_t Vddr1DynamicPower;
|
||
|
|
uint32_t spare[8];
|
||
|
|
uint32_t temperature;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_Discrete_Cac_Verification_Table SMU71_Discrete_Cac_Verification_Table;
|
||
|
|
|
||
|
|
#if !defined(SMC_MICROCODE)
|
||
|
|
#pragma pack(pop)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|