539 lines
16 KiB
C
539 lines
16 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014-2018 Etnaviv Project
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*/
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#include <drm/drm_drv.h>
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#include "etnaviv_cmdbuf.h"
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#include "etnaviv_gpu.h"
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#include "etnaviv_gem.h"
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#include "etnaviv_mmu.h"
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#include "common.xml.h"
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#include "state.xml.h"
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#include "state_blt.xml.h"
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#include "state_hi.xml.h"
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#include "state_3d.xml.h"
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#include "cmdstream.xml.h"
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/*
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* Command Buffer helper:
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*/
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static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data)
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{
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u32 *vaddr = (u32 *)buffer->vaddr;
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BUG_ON(buffer->user_size >= buffer->size);
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vaddr[buffer->user_size / 4] = data;
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buffer->user_size += 4;
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}
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static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer,
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u32 reg, u32 value)
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{
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u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR;
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buffer->user_size = ALIGN(buffer->user_size, 8);
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/* write a register via cmd stream */
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OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE |
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VIV_FE_LOAD_STATE_HEADER_COUNT(1) |
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VIV_FE_LOAD_STATE_HEADER_OFFSET(index));
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OUT(buffer, value);
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}
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static inline void CMD_END(struct etnaviv_cmdbuf *buffer)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_END_HEADER_OP_END);
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}
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static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT | 200);
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}
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static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer,
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u16 prefetch, u32 address)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK |
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VIV_FE_LINK_HEADER_PREFETCH(prefetch));
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OUT(buffer, address);
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}
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static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer,
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u32 from, u32 to)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL);
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OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
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}
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static inline void CMD_SEM(struct etnaviv_cmdbuf *buffer, u32 from, u32 to)
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{
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CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN,
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VIVS_GL_SEMAPHORE_TOKEN_FROM(from) |
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VIVS_GL_SEMAPHORE_TOKEN_TO(to));
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}
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static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buffer, u8 pipe)
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{
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u32 flush = 0;
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lockdep_assert_held(&gpu->lock);
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/*
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* This assumes that if we're switching to 2D, we're switching
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* away from 3D, and vice versa. Hence, if we're switching to
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* the 2D core, we need to flush the 3D depth and color caches,
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* otherwise we need to flush the 2D pixel engine cache.
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*/
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if (gpu->exec_state == ETNA_PIPE_2D)
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flush = VIVS_GL_FLUSH_CACHE_PE2D;
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else if (gpu->exec_state == ETNA_PIPE_3D)
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flush = VIVS_GL_FLUSH_CACHE_DEPTH | VIVS_GL_FLUSH_CACHE_COLOR;
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CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
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VIVS_GL_PIPE_SELECT_PIPE(pipe));
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}
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static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buf, u32 off, u32 len)
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{
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u32 size = buf->size;
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u32 *ptr = buf->vaddr + off;
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dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
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ptr, etnaviv_cmdbuf_get_va(buf,
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&gpu->mmu_context->cmdbuf_mapping) +
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off, size - len * 4 - off);
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print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
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ptr, len * 4, 0);
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}
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/*
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* Safely replace the WAIT of a waitlink with a new command and argument.
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* The GPU may be executing this WAIT while we're modifying it, so we have
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* to write it in a specific order to avoid the GPU branching to somewhere
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* else. 'wl_offset' is the offset to the first byte of the WAIT command.
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*/
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static void etnaviv_buffer_replace_wait(struct etnaviv_cmdbuf *buffer,
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unsigned int wl_offset, u32 cmd, u32 arg)
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{
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u32 *lw = buffer->vaddr + wl_offset;
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lw[1] = arg;
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mb();
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lw[0] = cmd;
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mb();
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}
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/*
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* Ensure that there is space in the command buffer to contiguously write
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* 'cmd_dwords' 64-bit words into the buffer, wrapping if necessary.
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*/
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static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buffer, unsigned int cmd_dwords)
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{
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if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size)
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buffer->user_size = 0;
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return etnaviv_cmdbuf_get_va(buffer,
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&gpu->mmu_context->cmdbuf_mapping) +
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buffer->user_size;
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}
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u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_cmdbuf *buffer = &gpu->buffer;
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lockdep_assert_held(&gpu->lock);
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/* initialize buffer */
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buffer->user_size = 0;
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CMD_WAIT(buffer);
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CMD_LINK(buffer, 2,
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etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
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+ buffer->user_size - 4);
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return buffer->user_size / 8;
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}
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u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr)
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{
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struct etnaviv_cmdbuf *buffer = &gpu->buffer;
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lockdep_assert_held(&gpu->lock);
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buffer->user_size = 0;
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if (gpu->identity.features & chipFeatures_PIPE_3D) {
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CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
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VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_3D));
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CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
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mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
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CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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}
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if (gpu->identity.features & chipFeatures_PIPE_2D) {
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CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
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VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_2D));
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CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
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mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
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CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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}
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CMD_END(buffer);
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buffer->user_size = ALIGN(buffer->user_size, 8);
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return buffer->user_size / 8;
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}
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u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id)
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{
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struct etnaviv_cmdbuf *buffer = &gpu->buffer;
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lockdep_assert_held(&gpu->lock);
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buffer->user_size = 0;
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CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG,
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VIVS_MMUv2_PTA_CONFIG_INDEX(id));
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CMD_END(buffer);
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buffer->user_size = ALIGN(buffer->user_size, 8);
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return buffer->user_size / 8;
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}
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void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_cmdbuf *buffer = &gpu->buffer;
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unsigned int waitlink_offset = buffer->user_size - 16;
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u32 link_target, flush = 0;
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bool has_blt = !!(gpu->identity.minor_features5 &
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chipMinorFeatures5_BLT_ENGINE);
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lockdep_assert_held(&gpu->lock);
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if (gpu->exec_state == ETNA_PIPE_2D)
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flush = VIVS_GL_FLUSH_CACHE_PE2D;
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else if (gpu->exec_state == ETNA_PIPE_3D)
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flush = VIVS_GL_FLUSH_CACHE_DEPTH |
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VIVS_GL_FLUSH_CACHE_COLOR |
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VIVS_GL_FLUSH_CACHE_TEXTURE |
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VIVS_GL_FLUSH_CACHE_TEXTUREVS |
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VIVS_GL_FLUSH_CACHE_SHADER_L2;
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if (flush) {
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unsigned int dwords = 7;
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if (has_blt)
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dwords += 10;
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link_target = etnaviv_buffer_reserve(gpu, buffer, dwords);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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if (has_blt) {
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CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
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CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
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}
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CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
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if (gpu->exec_state == ETNA_PIPE_3D) {
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if (has_blt) {
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CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
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CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1);
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CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
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} else {
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CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
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VIVS_TS_FLUSH_CACHE_FLUSH);
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}
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}
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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if (has_blt) {
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CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
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CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
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}
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CMD_END(buffer);
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etnaviv_buffer_replace_wait(buffer, waitlink_offset,
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VIV_FE_LINK_HEADER_OP_LINK |
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VIV_FE_LINK_HEADER_PREFETCH(dwords),
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link_target);
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} else {
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/* Replace the last link-wait with an "END" command */
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etnaviv_buffer_replace_wait(buffer, waitlink_offset,
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VIV_FE_END_HEADER_OP_END, 0);
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}
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}
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/* Append a 'sync point' to the ring buffer. */
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void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event)
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{
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struct etnaviv_cmdbuf *buffer = &gpu->buffer;
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unsigned int waitlink_offset = buffer->user_size - 16;
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u32 dwords, target;
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lockdep_assert_held(&gpu->lock);
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/*
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* We need at most 3 dwords in the return target:
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* 1 event + 1 end + 1 wait + 1 link.
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*/
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dwords = 4;
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target = etnaviv_buffer_reserve(gpu, buffer, dwords);
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/* Signal sync point event */
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CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
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VIVS_GL_EVENT_FROM_PE);
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/* Stop the FE to 'pause' the GPU */
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CMD_END(buffer);
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/* Append waitlink */
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CMD_WAIT(buffer);
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CMD_LINK(buffer, 2,
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etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
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+ buffer->user_size - 4);
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/*
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* Kick off the 'sync point' command by replacing the previous
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* WAIT with a link to the address in the ring buffer.
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*/
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etnaviv_buffer_replace_wait(buffer, waitlink_offset,
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VIV_FE_LINK_HEADER_OP_LINK |
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VIV_FE_LINK_HEADER_PREFETCH(dwords),
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target);
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}
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/* Append a command buffer to the ring buffer. */
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void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
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struct etnaviv_iommu_context *mmu_context, unsigned int event,
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struct etnaviv_cmdbuf *cmdbuf)
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{
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struct etnaviv_cmdbuf *buffer = &gpu->buffer;
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unsigned int waitlink_offset = buffer->user_size - 16;
|
||
|
|
u32 return_target, return_dwords;
|
||
|
|
u32 link_target, link_dwords;
|
||
|
|
bool switch_context = gpu->exec_state != exec_state;
|
||
|
|
bool switch_mmu_context = gpu->mmu_context != mmu_context;
|
||
|
|
unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
|
||
|
|
bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq;
|
||
|
|
bool has_blt = !!(gpu->identity.minor_features5 &
|
||
|
|
chipMinorFeatures5_BLT_ENGINE);
|
||
|
|
|
||
|
|
lockdep_assert_held(&gpu->lock);
|
||
|
|
|
||
|
|
if (drm_debug_enabled(DRM_UT_DRIVER))
|
||
|
|
etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
|
||
|
|
|
||
|
|
link_target = etnaviv_cmdbuf_get_va(cmdbuf,
|
||
|
|
&gpu->mmu_context->cmdbuf_mapping);
|
||
|
|
link_dwords = cmdbuf->size / 8;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If we need maintenance prior to submitting this buffer, we will
|
||
|
|
* need to append a mmu flush load state, followed by a new
|
||
|
|
* link to this buffer - a total of four additional words.
|
||
|
|
*/
|
||
|
|
if (need_flush || switch_context) {
|
||
|
|
u32 target, extra_dwords;
|
||
|
|
|
||
|
|
/* link command */
|
||
|
|
extra_dwords = 1;
|
||
|
|
|
||
|
|
/* flush command */
|
||
|
|
if (need_flush) {
|
||
|
|
if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1)
|
||
|
|
extra_dwords += 1;
|
||
|
|
else
|
||
|
|
extra_dwords += 3;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* pipe switch commands */
|
||
|
|
if (switch_context)
|
||
|
|
extra_dwords += 4;
|
||
|
|
|
||
|
|
/* PTA load command */
|
||
|
|
if (switch_mmu_context && gpu->sec_mode == ETNA_SEC_KERNEL)
|
||
|
|
extra_dwords += 1;
|
||
|
|
|
||
|
|
target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);
|
||
|
|
/*
|
||
|
|
* Switch MMU context if necessary. Must be done after the
|
||
|
|
* link target has been calculated, as the jump forward in the
|
||
|
|
* kernel ring still uses the last active MMU context before
|
||
|
|
* the switch.
|
||
|
|
*/
|
||
|
|
if (switch_mmu_context) {
|
||
|
|
struct etnaviv_iommu_context *old_context = gpu->mmu_context;
|
||
|
|
|
||
|
|
gpu->mmu_context = etnaviv_iommu_context_get(mmu_context);
|
||
|
|
etnaviv_iommu_context_put(old_context);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (need_flush) {
|
||
|
|
/* Add the MMU flush */
|
||
|
|
if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1) {
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
|
||
|
|
VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |
|
||
|
|
VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |
|
||
|
|
VIVS_GL_FLUSH_MMU_FLUSH_UNK2 |
|
||
|
|
VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |
|
||
|
|
VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
|
||
|
|
} else {
|
||
|
|
u32 flush = VIVS_MMUv2_CONFIGURATION_MODE_MASK |
|
||
|
|
VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH;
|
||
|
|
|
||
|
|
if (switch_mmu_context &&
|
||
|
|
gpu->sec_mode == ETNA_SEC_KERNEL) {
|
||
|
|
unsigned short id =
|
||
|
|
etnaviv_iommuv2_get_pta_id(gpu->mmu_context);
|
||
|
|
CMD_LOAD_STATE(buffer,
|
||
|
|
VIVS_MMUv2_PTA_CONFIG,
|
||
|
|
VIVS_MMUv2_PTA_CONFIG_INDEX(id));
|
||
|
|
}
|
||
|
|
|
||
|
|
if (gpu->sec_mode == ETNA_SEC_NONE)
|
||
|
|
flush |= etnaviv_iommuv2_get_mtlb_addr(gpu->mmu_context);
|
||
|
|
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
|
||
|
|
flush);
|
||
|
|
CMD_SEM(buffer, SYNC_RECIPIENT_FE,
|
||
|
|
SYNC_RECIPIENT_PE);
|
||
|
|
CMD_STALL(buffer, SYNC_RECIPIENT_FE,
|
||
|
|
SYNC_RECIPIENT_PE);
|
||
|
|
}
|
||
|
|
|
||
|
|
gpu->flush_seq = new_flush_seq;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (switch_context) {
|
||
|
|
etnaviv_cmd_select_pipe(gpu, buffer, exec_state);
|
||
|
|
gpu->exec_state = exec_state;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* And the link to the submitted buffer */
|
||
|
|
link_target = etnaviv_cmdbuf_get_va(cmdbuf,
|
||
|
|
&gpu->mmu_context->cmdbuf_mapping);
|
||
|
|
CMD_LINK(buffer, link_dwords, link_target);
|
||
|
|
|
||
|
|
/* Update the link target to point to above instructions */
|
||
|
|
link_target = target;
|
||
|
|
link_dwords = extra_dwords;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Append a LINK to the submitted command buffer to return to
|
||
|
|
* the ring buffer. return_target is the ring target address.
|
||
|
|
* We need at most 7 dwords in the return target: 2 cache flush +
|
||
|
|
* 2 semaphore stall + 1 event + 1 wait + 1 link.
|
||
|
|
*/
|
||
|
|
return_dwords = 7;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* When the BLT engine is present we need 6 more dwords in the return
|
||
|
|
* target: 3 enable/flush/disable + 4 enable/semaphore stall/disable,
|
||
|
|
* but we don't need the normal TS flush state.
|
||
|
|
*/
|
||
|
|
if (has_blt)
|
||
|
|
return_dwords += 6;
|
||
|
|
|
||
|
|
return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
|
||
|
|
CMD_LINK(cmdbuf, return_dwords, return_target);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Append a cache flush, stall, event, wait and link pointing back to
|
||
|
|
* the wait command to the ring buffer.
|
||
|
|
*/
|
||
|
|
if (gpu->exec_state == ETNA_PIPE_2D) {
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
|
||
|
|
VIVS_GL_FLUSH_CACHE_PE2D);
|
||
|
|
} else {
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
|
||
|
|
VIVS_GL_FLUSH_CACHE_DEPTH |
|
||
|
|
VIVS_GL_FLUSH_CACHE_COLOR);
|
||
|
|
if (has_blt) {
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1);
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
|
||
|
|
} else {
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
|
||
|
|
VIVS_TS_FLUSH_CACHE_FLUSH);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
|
||
|
|
CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
|
||
|
|
|
||
|
|
if (has_blt) {
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
|
||
|
|
CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
|
||
|
|
CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
|
||
|
|
}
|
||
|
|
|
||
|
|
CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
|
||
|
|
VIVS_GL_EVENT_FROM_PE);
|
||
|
|
CMD_WAIT(buffer);
|
||
|
|
CMD_LINK(buffer, 2,
|
||
|
|
etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
|
||
|
|
+ buffer->user_size - 4);
|
||
|
|
|
||
|
|
if (drm_debug_enabled(DRM_UT_DRIVER))
|
||
|
|
pr_info("stream link to 0x%08x @ 0x%08x %p\n",
|
||
|
|
return_target,
|
||
|
|
etnaviv_cmdbuf_get_va(cmdbuf, &gpu->mmu_context->cmdbuf_mapping),
|
||
|
|
cmdbuf->vaddr);
|
||
|
|
|
||
|
|
if (drm_debug_enabled(DRM_UT_DRIVER)) {
|
||
|
|
print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
|
||
|
|
cmdbuf->vaddr, cmdbuf->size, 0);
|
||
|
|
|
||
|
|
pr_info("link op: %p\n", buffer->vaddr + waitlink_offset);
|
||
|
|
pr_info("addr: 0x%08x\n", link_target);
|
||
|
|
pr_info("back: 0x%08x\n", return_target);
|
||
|
|
pr_info("event: %d\n", event);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Kick off the submitted command by replacing the previous
|
||
|
|
* WAIT with a link to the address in the ring buffer.
|
||
|
|
*/
|
||
|
|
etnaviv_buffer_replace_wait(buffer, waitlink_offset,
|
||
|
|
VIV_FE_LINK_HEADER_OP_LINK |
|
||
|
|
VIV_FE_LINK_HEADER_PREFETCH(link_dwords),
|
||
|
|
link_target);
|
||
|
|
|
||
|
|
if (drm_debug_enabled(DRM_UT_DRIVER))
|
||
|
|
etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
|
||
|
|
}
|