773 lines
17 KiB
C
773 lines
17 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/**************************************************************************
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* Copyright (c) 2007, Intel Corporation.
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*
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**************************************************************************/
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#include <linux/highmem.h>
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#include "mmu.h"
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#include "psb_drv.h"
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#include "psb_reg.h"
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/*
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* Code for the SGX MMU:
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*/
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/*
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* clflush on one processor only:
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* clflush should apparently flush the cache line on all processors in an
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* SMP system.
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*/
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/*
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* kmap atomic:
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* The usage of the slots must be completely encapsulated within a spinlock, and
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* no other functions that may be using the locks for other purposed may be
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* called from within the locked region.
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* Since the slots are per processor, this will guarantee that we are the only
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* user.
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*/
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/*
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* TODO: Inserting ptes from an interrupt handler:
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* This may be desirable for some SGX functionality where the GPU can fault in
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* needed pages. For that, we need to make an atomic insert_pages function, that
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* may fail.
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* If it fails, the caller need to insert the page using a workqueue function,
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* but on average it should be fast.
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*/
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static inline uint32_t psb_mmu_pt_index(uint32_t offset)
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{
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return (offset >> PSB_PTE_SHIFT) & 0x3FF;
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}
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static inline uint32_t psb_mmu_pd_index(uint32_t offset)
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{
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return offset >> PSB_PDE_SHIFT;
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}
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static inline void psb_clflush(void *addr)
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{
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__asm__ __volatile__("clflush (%0)\n" : : "r"(addr) : "memory");
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}
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static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
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{
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if (!driver->has_clflush)
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return;
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mb();
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psb_clflush(addr);
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mb();
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}
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static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver, int force)
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{
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struct drm_device *dev = driver->dev;
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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if (atomic_read(&driver->needs_tlbflush) || force) {
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uint32_t val = PSB_RSGX32(PSB_CR_BIF_CTRL);
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PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
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/* Make sure data cache is turned off before enabling it */
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wmb();
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PSB_WSGX32(val & ~_PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
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(void)PSB_RSGX32(PSB_CR_BIF_CTRL);
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if (driver->msvdx_mmu_invaldc)
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atomic_set(driver->msvdx_mmu_invaldc, 1);
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}
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atomic_set(&driver->needs_tlbflush, 0);
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}
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#if 0
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static void psb_mmu_flush_pd(struct psb_mmu_driver *driver, int force)
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{
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down_write(&driver->sem);
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psb_mmu_flush_pd_locked(driver, force);
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up_write(&driver->sem);
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}
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#endif
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void psb_mmu_flush(struct psb_mmu_driver *driver)
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{
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struct drm_device *dev = driver->dev;
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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uint32_t val;
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down_write(&driver->sem);
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val = PSB_RSGX32(PSB_CR_BIF_CTRL);
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if (atomic_read(&driver->needs_tlbflush))
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PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
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else
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PSB_WSGX32(val | _PSB_CB_CTRL_FLUSH, PSB_CR_BIF_CTRL);
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/* Make sure data cache is turned off and MMU is flushed before
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restoring bank interface control register */
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wmb();
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PSB_WSGX32(val & ~(_PSB_CB_CTRL_FLUSH | _PSB_CB_CTRL_INVALDC),
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PSB_CR_BIF_CTRL);
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(void)PSB_RSGX32(PSB_CR_BIF_CTRL);
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atomic_set(&driver->needs_tlbflush, 0);
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if (driver->msvdx_mmu_invaldc)
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atomic_set(driver->msvdx_mmu_invaldc, 1);
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up_write(&driver->sem);
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}
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void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
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{
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struct drm_device *dev = pd->driver->dev;
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 :
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PSB_CR_BIF_DIR_LIST_BASE1 + hw_context * 4;
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down_write(&pd->driver->sem);
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PSB_WSGX32(page_to_pfn(pd->p) << PAGE_SHIFT, offset);
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wmb();
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psb_mmu_flush_pd_locked(pd->driver, 1);
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pd->hw_context = hw_context;
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up_write(&pd->driver->sem);
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}
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static inline unsigned long psb_pd_addr_end(unsigned long addr,
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unsigned long end)
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{
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addr = (addr + PSB_PDE_MASK + 1) & ~PSB_PDE_MASK;
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return (addr < end) ? addr : end;
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}
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static inline uint32_t psb_mmu_mask_pte(uint32_t pfn, int type)
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{
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uint32_t mask = PSB_PTE_VALID;
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if (type & PSB_MMU_CACHED_MEMORY)
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mask |= PSB_PTE_CACHED;
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if (type & PSB_MMU_RO_MEMORY)
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mask |= PSB_PTE_RO;
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if (type & PSB_MMU_WO_MEMORY)
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mask |= PSB_PTE_WO;
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return (pfn << PAGE_SHIFT) | mask;
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}
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struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
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int trap_pagefaults, int invalid_type)
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{
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struct psb_mmu_pd *pd = kmalloc(sizeof(*pd), GFP_KERNEL);
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uint32_t *v;
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int i;
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if (!pd)
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return NULL;
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pd->p = alloc_page(GFP_DMA32);
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if (!pd->p)
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goto out_err1;
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pd->dummy_pt = alloc_page(GFP_DMA32);
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if (!pd->dummy_pt)
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goto out_err2;
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pd->dummy_page = alloc_page(GFP_DMA32);
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if (!pd->dummy_page)
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goto out_err3;
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if (!trap_pagefaults) {
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pd->invalid_pde = psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
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invalid_type);
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pd->invalid_pte = psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
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invalid_type);
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} else {
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pd->invalid_pde = 0;
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pd->invalid_pte = 0;
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}
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v = kmap_local_page(pd->dummy_pt);
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for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
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v[i] = pd->invalid_pte;
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kunmap_local(v);
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v = kmap_local_page(pd->p);
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for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
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v[i] = pd->invalid_pde;
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kunmap_local(v);
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clear_page(kmap(pd->dummy_page));
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kunmap(pd->dummy_page);
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pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
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if (!pd->tables)
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goto out_err4;
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pd->hw_context = -1;
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pd->pd_mask = PSB_PTE_VALID;
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pd->driver = driver;
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return pd;
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out_err4:
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__free_page(pd->dummy_page);
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out_err3:
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__free_page(pd->dummy_pt);
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out_err2:
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__free_page(pd->p);
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out_err1:
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kfree(pd);
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return NULL;
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}
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static void psb_mmu_free_pt(struct psb_mmu_pt *pt)
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{
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__free_page(pt->p);
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kfree(pt);
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}
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void psb_mmu_free_pagedir(struct psb_mmu_pd *pd)
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{
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struct psb_mmu_driver *driver = pd->driver;
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struct drm_device *dev = driver->dev;
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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struct psb_mmu_pt *pt;
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int i;
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down_write(&driver->sem);
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if (pd->hw_context != -1) {
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PSB_WSGX32(0, PSB_CR_BIF_DIR_LIST_BASE0 + pd->hw_context * 4);
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psb_mmu_flush_pd_locked(driver, 1);
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}
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/* Should take the spinlock here, but we don't need to do that
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since we have the semaphore in write mode. */
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for (i = 0; i < 1024; ++i) {
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pt = pd->tables[i];
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if (pt)
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psb_mmu_free_pt(pt);
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}
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vfree(pd->tables);
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__free_page(pd->dummy_page);
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__free_page(pd->dummy_pt);
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__free_page(pd->p);
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kfree(pd);
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up_write(&driver->sem);
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}
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static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
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{
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struct psb_mmu_pt *pt = kmalloc(sizeof(*pt), GFP_KERNEL);
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void *v;
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uint32_t clflush_add = pd->driver->clflush_add >> PAGE_SHIFT;
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uint32_t clflush_count = PAGE_SIZE / clflush_add;
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spinlock_t *lock = &pd->driver->lock;
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uint8_t *clf;
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uint32_t *ptes;
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int i;
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if (!pt)
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return NULL;
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pt->p = alloc_page(GFP_DMA32);
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if (!pt->p) {
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kfree(pt);
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return NULL;
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}
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spin_lock(lock);
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v = kmap_atomic(pt->p);
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clf = (uint8_t *) v;
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ptes = (uint32_t *) v;
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for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
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*ptes++ = pd->invalid_pte;
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if (pd->driver->has_clflush && pd->hw_context != -1) {
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mb();
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for (i = 0; i < clflush_count; ++i) {
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psb_clflush(clf);
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clf += clflush_add;
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}
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mb();
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}
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kunmap_atomic(v);
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spin_unlock(lock);
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pt->count = 0;
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pt->pd = pd;
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pt->index = 0;
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return pt;
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}
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static struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
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unsigned long addr)
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{
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uint32_t index = psb_mmu_pd_index(addr);
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struct psb_mmu_pt *pt;
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uint32_t *v;
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spinlock_t *lock = &pd->driver->lock;
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spin_lock(lock);
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pt = pd->tables[index];
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while (!pt) {
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spin_unlock(lock);
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pt = psb_mmu_alloc_pt(pd);
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if (!pt)
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return NULL;
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spin_lock(lock);
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if (pd->tables[index]) {
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spin_unlock(lock);
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psb_mmu_free_pt(pt);
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spin_lock(lock);
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pt = pd->tables[index];
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continue;
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}
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v = kmap_atomic(pd->p);
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pd->tables[index] = pt;
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v[index] = (page_to_pfn(pt->p) << 12) | pd->pd_mask;
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pt->index = index;
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kunmap_atomic((void *) v);
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if (pd->hw_context != -1) {
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psb_mmu_clflush(pd->driver, (void *)&v[index]);
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atomic_set(&pd->driver->needs_tlbflush, 1);
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}
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}
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pt->v = kmap_atomic(pt->p);
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return pt;
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}
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static struct psb_mmu_pt *psb_mmu_pt_map_lock(struct psb_mmu_pd *pd,
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unsigned long addr)
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{
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uint32_t index = psb_mmu_pd_index(addr);
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struct psb_mmu_pt *pt;
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spinlock_t *lock = &pd->driver->lock;
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spin_lock(lock);
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pt = pd->tables[index];
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if (!pt) {
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spin_unlock(lock);
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return NULL;
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}
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pt->v = kmap_atomic(pt->p);
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return pt;
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}
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static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
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{
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struct psb_mmu_pd *pd = pt->pd;
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uint32_t *v;
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kunmap_atomic(pt->v);
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|
if (pt->count == 0) {
|
||
|
|
v = kmap_atomic(pd->p);
|
||
|
|
v[pt->index] = pd->invalid_pde;
|
||
|
|
pd->tables[pt->index] = NULL;
|
||
|
|
|
||
|
|
if (pd->hw_context != -1) {
|
||
|
|
psb_mmu_clflush(pd->driver, (void *)&v[pt->index]);
|
||
|
|
atomic_set(&pd->driver->needs_tlbflush, 1);
|
||
|
|
}
|
||
|
|
kunmap_atomic(v);
|
||
|
|
spin_unlock(&pd->driver->lock);
|
||
|
|
psb_mmu_free_pt(pt);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
spin_unlock(&pd->driver->lock);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt, unsigned long addr,
|
||
|
|
uint32_t pte)
|
||
|
|
{
|
||
|
|
pt->v[psb_mmu_pt_index(addr)] = pte;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt,
|
||
|
|
unsigned long addr)
|
||
|
|
{
|
||
|
|
pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver)
|
||
|
|
{
|
||
|
|
struct psb_mmu_pd *pd;
|
||
|
|
|
||
|
|
down_read(&driver->sem);
|
||
|
|
pd = driver->default_pd;
|
||
|
|
up_read(&driver->sem);
|
||
|
|
|
||
|
|
return pd;
|
||
|
|
}
|
||
|
|
|
||
|
|
void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
|
||
|
|
{
|
||
|
|
struct drm_device *dev = driver->dev;
|
||
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
||
|
|
|
||
|
|
PSB_WSGX32(driver->bif_ctrl, PSB_CR_BIF_CTRL);
|
||
|
|
psb_mmu_free_pagedir(driver->default_pd);
|
||
|
|
kfree(driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev,
|
||
|
|
int trap_pagefaults,
|
||
|
|
int invalid_type,
|
||
|
|
atomic_t *msvdx_mmu_invaldc)
|
||
|
|
{
|
||
|
|
struct psb_mmu_driver *driver;
|
||
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
||
|
|
|
||
|
|
driver = kmalloc(sizeof(*driver), GFP_KERNEL);
|
||
|
|
|
||
|
|
if (!driver)
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
driver->dev = dev;
|
||
|
|
driver->default_pd = psb_mmu_alloc_pd(driver, trap_pagefaults,
|
||
|
|
invalid_type);
|
||
|
|
if (!driver->default_pd)
|
||
|
|
goto out_err1;
|
||
|
|
|
||
|
|
spin_lock_init(&driver->lock);
|
||
|
|
init_rwsem(&driver->sem);
|
||
|
|
down_write(&driver->sem);
|
||
|
|
atomic_set(&driver->needs_tlbflush, 1);
|
||
|
|
driver->msvdx_mmu_invaldc = msvdx_mmu_invaldc;
|
||
|
|
|
||
|
|
driver->bif_ctrl = PSB_RSGX32(PSB_CR_BIF_CTRL);
|
||
|
|
PSB_WSGX32(driver->bif_ctrl | _PSB_CB_CTRL_CLEAR_FAULT,
|
||
|
|
PSB_CR_BIF_CTRL);
|
||
|
|
PSB_WSGX32(driver->bif_ctrl & ~_PSB_CB_CTRL_CLEAR_FAULT,
|
||
|
|
PSB_CR_BIF_CTRL);
|
||
|
|
|
||
|
|
driver->has_clflush = 0;
|
||
|
|
|
||
|
|
if (boot_cpu_has(X86_FEATURE_CLFLUSH)) {
|
||
|
|
uint32_t tfms, misc, cap0, cap4, clflush_size;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* clflush size is determined at kernel setup for x86_64 but not
|
||
|
|
* for i386. We have to do it here.
|
||
|
|
*/
|
||
|
|
|
||
|
|
cpuid(0x00000001, &tfms, &misc, &cap0, &cap4);
|
||
|
|
clflush_size = ((misc >> 8) & 0xff) * 8;
|
||
|
|
driver->has_clflush = 1;
|
||
|
|
driver->clflush_add =
|
||
|
|
PAGE_SIZE * clflush_size / sizeof(uint32_t);
|
||
|
|
driver->clflush_mask = driver->clflush_add - 1;
|
||
|
|
driver->clflush_mask = ~driver->clflush_mask;
|
||
|
|
}
|
||
|
|
|
||
|
|
up_write(&driver->sem);
|
||
|
|
return driver;
|
||
|
|
|
||
|
|
out_err1:
|
||
|
|
kfree(driver);
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
|
||
|
|
uint32_t num_pages, uint32_t desired_tile_stride,
|
||
|
|
uint32_t hw_tile_stride)
|
||
|
|
{
|
||
|
|
struct psb_mmu_pt *pt;
|
||
|
|
uint32_t rows = 1;
|
||
|
|
uint32_t i;
|
||
|
|
unsigned long addr;
|
||
|
|
unsigned long end;
|
||
|
|
unsigned long next;
|
||
|
|
unsigned long add;
|
||
|
|
unsigned long row_add;
|
||
|
|
unsigned long clflush_add = pd->driver->clflush_add;
|
||
|
|
unsigned long clflush_mask = pd->driver->clflush_mask;
|
||
|
|
|
||
|
|
if (!pd->driver->has_clflush)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (hw_tile_stride)
|
||
|
|
rows = num_pages / desired_tile_stride;
|
||
|
|
else
|
||
|
|
desired_tile_stride = num_pages;
|
||
|
|
|
||
|
|
add = desired_tile_stride << PAGE_SHIFT;
|
||
|
|
row_add = hw_tile_stride << PAGE_SHIFT;
|
||
|
|
mb();
|
||
|
|
for (i = 0; i < rows; ++i) {
|
||
|
|
|
||
|
|
addr = address;
|
||
|
|
end = addr + add;
|
||
|
|
|
||
|
|
do {
|
||
|
|
next = psb_pd_addr_end(addr, end);
|
||
|
|
pt = psb_mmu_pt_map_lock(pd, addr);
|
||
|
|
if (!pt)
|
||
|
|
continue;
|
||
|
|
do {
|
||
|
|
psb_clflush(&pt->v[psb_mmu_pt_index(addr)]);
|
||
|
|
} while (addr += clflush_add,
|
||
|
|
(addr & clflush_mask) < next);
|
||
|
|
|
||
|
|
psb_mmu_pt_unmap_unlock(pt);
|
||
|
|
} while (addr = next, next != end);
|
||
|
|
address += row_add;
|
||
|
|
}
|
||
|
|
mb();
|
||
|
|
}
|
||
|
|
|
||
|
|
void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
|
||
|
|
unsigned long address, uint32_t num_pages)
|
||
|
|
{
|
||
|
|
struct psb_mmu_pt *pt;
|
||
|
|
unsigned long addr;
|
||
|
|
unsigned long end;
|
||
|
|
unsigned long next;
|
||
|
|
unsigned long f_address = address;
|
||
|
|
|
||
|
|
down_read(&pd->driver->sem);
|
||
|
|
|
||
|
|
addr = address;
|
||
|
|
end = addr + (num_pages << PAGE_SHIFT);
|
||
|
|
|
||
|
|
do {
|
||
|
|
next = psb_pd_addr_end(addr, end);
|
||
|
|
pt = psb_mmu_pt_alloc_map_lock(pd, addr);
|
||
|
|
if (!pt)
|
||
|
|
goto out;
|
||
|
|
do {
|
||
|
|
psb_mmu_invalidate_pte(pt, addr);
|
||
|
|
--pt->count;
|
||
|
|
} while (addr += PAGE_SIZE, addr < next);
|
||
|
|
psb_mmu_pt_unmap_unlock(pt);
|
||
|
|
|
||
|
|
} while (addr = next, next != end);
|
||
|
|
|
||
|
|
out:
|
||
|
|
if (pd->hw_context != -1)
|
||
|
|
psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
|
||
|
|
|
||
|
|
up_read(&pd->driver->sem);
|
||
|
|
|
||
|
|
if (pd->hw_context != -1)
|
||
|
|
psb_mmu_flush(pd->driver);
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
|
||
|
|
uint32_t num_pages, uint32_t desired_tile_stride,
|
||
|
|
uint32_t hw_tile_stride)
|
||
|
|
{
|
||
|
|
struct psb_mmu_pt *pt;
|
||
|
|
uint32_t rows = 1;
|
||
|
|
uint32_t i;
|
||
|
|
unsigned long addr;
|
||
|
|
unsigned long end;
|
||
|
|
unsigned long next;
|
||
|
|
unsigned long add;
|
||
|
|
unsigned long row_add;
|
||
|
|
unsigned long f_address = address;
|
||
|
|
|
||
|
|
if (hw_tile_stride)
|
||
|
|
rows = num_pages / desired_tile_stride;
|
||
|
|
else
|
||
|
|
desired_tile_stride = num_pages;
|
||
|
|
|
||
|
|
add = desired_tile_stride << PAGE_SHIFT;
|
||
|
|
row_add = hw_tile_stride << PAGE_SHIFT;
|
||
|
|
|
||
|
|
down_read(&pd->driver->sem);
|
||
|
|
|
||
|
|
/* Make sure we only need to flush this processor's cache */
|
||
|
|
|
||
|
|
for (i = 0; i < rows; ++i) {
|
||
|
|
|
||
|
|
addr = address;
|
||
|
|
end = addr + add;
|
||
|
|
|
||
|
|
do {
|
||
|
|
next = psb_pd_addr_end(addr, end);
|
||
|
|
pt = psb_mmu_pt_map_lock(pd, addr);
|
||
|
|
if (!pt)
|
||
|
|
continue;
|
||
|
|
do {
|
||
|
|
psb_mmu_invalidate_pte(pt, addr);
|
||
|
|
--pt->count;
|
||
|
|
|
||
|
|
} while (addr += PAGE_SIZE, addr < next);
|
||
|
|
psb_mmu_pt_unmap_unlock(pt);
|
||
|
|
|
||
|
|
} while (addr = next, next != end);
|
||
|
|
address += row_add;
|
||
|
|
}
|
||
|
|
if (pd->hw_context != -1)
|
||
|
|
psb_mmu_flush_ptes(pd, f_address, num_pages,
|
||
|
|
desired_tile_stride, hw_tile_stride);
|
||
|
|
|
||
|
|
up_read(&pd->driver->sem);
|
||
|
|
|
||
|
|
if (pd->hw_context != -1)
|
||
|
|
psb_mmu_flush(pd->driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
|
||
|
|
unsigned long address, uint32_t num_pages,
|
||
|
|
int type)
|
||
|
|
{
|
||
|
|
struct psb_mmu_pt *pt;
|
||
|
|
uint32_t pte;
|
||
|
|
unsigned long addr;
|
||
|
|
unsigned long end;
|
||
|
|
unsigned long next;
|
||
|
|
unsigned long f_address = address;
|
||
|
|
int ret = -ENOMEM;
|
||
|
|
|
||
|
|
down_read(&pd->driver->sem);
|
||
|
|
|
||
|
|
addr = address;
|
||
|
|
end = addr + (num_pages << PAGE_SHIFT);
|
||
|
|
|
||
|
|
do {
|
||
|
|
next = psb_pd_addr_end(addr, end);
|
||
|
|
pt = psb_mmu_pt_alloc_map_lock(pd, addr);
|
||
|
|
if (!pt) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
do {
|
||
|
|
pte = psb_mmu_mask_pte(start_pfn++, type);
|
||
|
|
psb_mmu_set_pte(pt, addr, pte);
|
||
|
|
pt->count++;
|
||
|
|
} while (addr += PAGE_SIZE, addr < next);
|
||
|
|
psb_mmu_pt_unmap_unlock(pt);
|
||
|
|
|
||
|
|
} while (addr = next, next != end);
|
||
|
|
ret = 0;
|
||
|
|
|
||
|
|
out:
|
||
|
|
if (pd->hw_context != -1)
|
||
|
|
psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
|
||
|
|
|
||
|
|
up_read(&pd->driver->sem);
|
||
|
|
|
||
|
|
if (pd->hw_context != -1)
|
||
|
|
psb_mmu_flush(pd->driver);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
|
||
|
|
unsigned long address, uint32_t num_pages,
|
||
|
|
uint32_t desired_tile_stride, uint32_t hw_tile_stride,
|
||
|
|
int type)
|
||
|
|
{
|
||
|
|
struct psb_mmu_pt *pt;
|
||
|
|
uint32_t rows = 1;
|
||
|
|
uint32_t i;
|
||
|
|
uint32_t pte;
|
||
|
|
unsigned long addr;
|
||
|
|
unsigned long end;
|
||
|
|
unsigned long next;
|
||
|
|
unsigned long add;
|
||
|
|
unsigned long row_add;
|
||
|
|
unsigned long f_address = address;
|
||
|
|
int ret = -ENOMEM;
|
||
|
|
|
||
|
|
if (hw_tile_stride) {
|
||
|
|
if (num_pages % desired_tile_stride != 0)
|
||
|
|
return -EINVAL;
|
||
|
|
rows = num_pages / desired_tile_stride;
|
||
|
|
} else {
|
||
|
|
desired_tile_stride = num_pages;
|
||
|
|
}
|
||
|
|
|
||
|
|
add = desired_tile_stride << PAGE_SHIFT;
|
||
|
|
row_add = hw_tile_stride << PAGE_SHIFT;
|
||
|
|
|
||
|
|
down_read(&pd->driver->sem);
|
||
|
|
|
||
|
|
for (i = 0; i < rows; ++i) {
|
||
|
|
|
||
|
|
addr = address;
|
||
|
|
end = addr + add;
|
||
|
|
|
||
|
|
do {
|
||
|
|
next = psb_pd_addr_end(addr, end);
|
||
|
|
pt = psb_mmu_pt_alloc_map_lock(pd, addr);
|
||
|
|
if (!pt)
|
||
|
|
goto out;
|
||
|
|
do {
|
||
|
|
pte = psb_mmu_mask_pte(page_to_pfn(*pages++),
|
||
|
|
type);
|
||
|
|
psb_mmu_set_pte(pt, addr, pte);
|
||
|
|
pt->count++;
|
||
|
|
} while (addr += PAGE_SIZE, addr < next);
|
||
|
|
psb_mmu_pt_unmap_unlock(pt);
|
||
|
|
|
||
|
|
} while (addr = next, next != end);
|
||
|
|
|
||
|
|
address += row_add;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = 0;
|
||
|
|
out:
|
||
|
|
if (pd->hw_context != -1)
|
||
|
|
psb_mmu_flush_ptes(pd, f_address, num_pages,
|
||
|
|
desired_tile_stride, hw_tile_stride);
|
||
|
|
|
||
|
|
up_read(&pd->driver->sem);
|
||
|
|
|
||
|
|
if (pd->hw_context != -1)
|
||
|
|
psb_mmu_flush(pd->driver);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
|
||
|
|
unsigned long *pfn)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
struct psb_mmu_pt *pt;
|
||
|
|
uint32_t tmp;
|
||
|
|
spinlock_t *lock = &pd->driver->lock;
|
||
|
|
|
||
|
|
down_read(&pd->driver->sem);
|
||
|
|
pt = psb_mmu_pt_map_lock(pd, virtual);
|
||
|
|
if (!pt) {
|
||
|
|
uint32_t *v;
|
||
|
|
|
||
|
|
spin_lock(lock);
|
||
|
|
v = kmap_atomic(pd->p);
|
||
|
|
tmp = v[psb_mmu_pd_index(virtual)];
|
||
|
|
kunmap_atomic(v);
|
||
|
|
spin_unlock(lock);
|
||
|
|
|
||
|
|
if (tmp != pd->invalid_pde || !(tmp & PSB_PTE_VALID) ||
|
||
|
|
!(pd->invalid_pte & PSB_PTE_VALID)) {
|
||
|
|
ret = -EINVAL;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
ret = 0;
|
||
|
|
*pfn = pd->invalid_pte >> PAGE_SHIFT;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
tmp = pt->v[psb_mmu_pt_index(virtual)];
|
||
|
|
if (!(tmp & PSB_PTE_VALID)) {
|
||
|
|
ret = -EINVAL;
|
||
|
|
} else {
|
||
|
|
ret = 0;
|
||
|
|
*pfn = tmp >> PAGE_SHIFT;
|
||
|
|
}
|
||
|
|
psb_mmu_pt_unmap_unlock(pt);
|
||
|
|
out:
|
||
|
|
up_read(&pd->driver->sem);
|
||
|
|
return ret;
|
||
|
|
}
|