289 lines
8.9 KiB
C
289 lines
8.9 KiB
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DISPLAY_POWER_H__
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#define __INTEL_DISPLAY_POWER_H__
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#include "intel_wakeref.h"
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enum aux_ch;
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enum dpio_channel;
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enum dpio_phy;
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enum i915_drm_suspend_mode;
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enum port;
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struct drm_i915_private;
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struct i915_power_well;
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struct intel_encoder;
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/*
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* Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
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* consecutive, so that the pipe,transcoder,port -> power domain macros
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* work correctly.
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*/
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enum intel_display_power_domain {
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POWER_DOMAIN_DISPLAY_CORE,
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POWER_DOMAIN_PIPE_A,
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POWER_DOMAIN_PIPE_B,
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POWER_DOMAIN_PIPE_C,
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POWER_DOMAIN_PIPE_D,
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POWER_DOMAIN_PIPE_PANEL_FITTER_A,
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POWER_DOMAIN_PIPE_PANEL_FITTER_B,
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POWER_DOMAIN_PIPE_PANEL_FITTER_C,
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POWER_DOMAIN_PIPE_PANEL_FITTER_D,
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POWER_DOMAIN_TRANSCODER_A,
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POWER_DOMAIN_TRANSCODER_B,
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POWER_DOMAIN_TRANSCODER_C,
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POWER_DOMAIN_TRANSCODER_D,
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POWER_DOMAIN_TRANSCODER_EDP,
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POWER_DOMAIN_TRANSCODER_DSI_A,
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POWER_DOMAIN_TRANSCODER_DSI_C,
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/* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
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POWER_DOMAIN_TRANSCODER_VDSC_PW2,
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POWER_DOMAIN_PORT_DDI_LANES_A,
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POWER_DOMAIN_PORT_DDI_LANES_B,
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POWER_DOMAIN_PORT_DDI_LANES_C,
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POWER_DOMAIN_PORT_DDI_LANES_D,
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POWER_DOMAIN_PORT_DDI_LANES_E,
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POWER_DOMAIN_PORT_DDI_LANES_F,
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POWER_DOMAIN_PORT_DDI_LANES_TC1,
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POWER_DOMAIN_PORT_DDI_LANES_TC2,
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POWER_DOMAIN_PORT_DDI_LANES_TC3,
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POWER_DOMAIN_PORT_DDI_LANES_TC4,
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POWER_DOMAIN_PORT_DDI_LANES_TC5,
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POWER_DOMAIN_PORT_DDI_LANES_TC6,
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POWER_DOMAIN_PORT_DDI_IO_A,
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POWER_DOMAIN_PORT_DDI_IO_B,
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POWER_DOMAIN_PORT_DDI_IO_C,
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POWER_DOMAIN_PORT_DDI_IO_D,
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POWER_DOMAIN_PORT_DDI_IO_E,
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POWER_DOMAIN_PORT_DDI_IO_F,
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POWER_DOMAIN_PORT_DDI_IO_TC1,
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POWER_DOMAIN_PORT_DDI_IO_TC2,
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POWER_DOMAIN_PORT_DDI_IO_TC3,
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POWER_DOMAIN_PORT_DDI_IO_TC4,
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POWER_DOMAIN_PORT_DDI_IO_TC5,
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POWER_DOMAIN_PORT_DDI_IO_TC6,
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POWER_DOMAIN_PORT_DSI,
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POWER_DOMAIN_PORT_CRT,
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POWER_DOMAIN_PORT_OTHER,
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POWER_DOMAIN_VGA,
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POWER_DOMAIN_AUDIO_MMIO,
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POWER_DOMAIN_AUDIO_PLAYBACK,
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POWER_DOMAIN_AUX_IO_A,
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POWER_DOMAIN_AUX_IO_B,
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POWER_DOMAIN_AUX_IO_C,
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POWER_DOMAIN_AUX_IO_D,
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POWER_DOMAIN_AUX_IO_E,
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POWER_DOMAIN_AUX_IO_F,
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POWER_DOMAIN_AUX_A,
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POWER_DOMAIN_AUX_B,
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POWER_DOMAIN_AUX_C,
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POWER_DOMAIN_AUX_D,
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POWER_DOMAIN_AUX_E,
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POWER_DOMAIN_AUX_F,
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POWER_DOMAIN_AUX_USBC1,
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POWER_DOMAIN_AUX_USBC2,
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POWER_DOMAIN_AUX_USBC3,
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POWER_DOMAIN_AUX_USBC4,
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POWER_DOMAIN_AUX_USBC5,
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POWER_DOMAIN_AUX_USBC6,
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POWER_DOMAIN_AUX_TBT1,
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POWER_DOMAIN_AUX_TBT2,
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POWER_DOMAIN_AUX_TBT3,
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POWER_DOMAIN_AUX_TBT4,
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POWER_DOMAIN_AUX_TBT5,
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POWER_DOMAIN_AUX_TBT6,
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POWER_DOMAIN_GMBUS,
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POWER_DOMAIN_MODESET,
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POWER_DOMAIN_GT_IRQ,
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POWER_DOMAIN_DC_OFF,
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POWER_DOMAIN_TC_COLD_OFF,
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POWER_DOMAIN_INIT,
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POWER_DOMAIN_NUM,
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POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
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};
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#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
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#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
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((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
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#define POWER_DOMAIN_TRANSCODER(tran) \
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((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
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(tran) + POWER_DOMAIN_TRANSCODER_A)
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struct intel_power_domain_mask {
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DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
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};
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struct i915_power_domains {
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/*
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* Power wells needed for initialization at driver init and suspend
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* time are on. They are kept on until after the first modeset.
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*/
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bool initializing;
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bool display_core_suspended;
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int power_well_count;
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intel_wakeref_t init_wakeref;
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intel_wakeref_t disable_wakeref;
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struct mutex lock;
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int domain_use_count[POWER_DOMAIN_NUM];
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struct delayed_work async_put_work;
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intel_wakeref_t async_put_wakeref;
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struct intel_power_domain_mask async_put_domains[2];
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struct i915_power_well *power_wells;
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};
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struct intel_display_power_domain_set {
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struct intel_power_domain_mask mask;
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#ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
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intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
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#endif
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};
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#define for_each_power_domain(__domain, __mask) \
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for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
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for_each_if(test_bit((__domain), (__mask)->bits))
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int intel_power_domains_init(struct drm_i915_private *dev_priv);
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void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
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void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
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void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
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void intel_power_domains_enable(struct drm_i915_private *dev_priv);
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void intel_power_domains_disable(struct drm_i915_private *dev_priv);
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void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
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enum i915_drm_suspend_mode);
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void intel_power_domains_resume(struct drm_i915_private *dev_priv);
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void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
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void intel_display_power_suspend_late(struct drm_i915_private *i915);
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void intel_display_power_resume_early(struct drm_i915_private *i915);
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void intel_display_power_suspend(struct drm_i915_private *i915);
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void intel_display_power_resume(struct drm_i915_private *i915);
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void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
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u32 state);
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const char *
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intel_display_power_domain_str(enum intel_display_power_domain domain);
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bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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intel_wakeref_t
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intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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void __intel_display_power_put_async(struct drm_i915_private *i915,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref);
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void intel_display_power_flush_work(struct drm_i915_private *i915);
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
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void intel_display_power_put(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref);
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static inline void
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intel_display_power_put_async(struct drm_i915_private *i915,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref)
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{
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__intel_display_power_put_async(i915, domain, wakeref);
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}
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#else
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void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain);
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static inline void
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intel_display_power_put(struct drm_i915_private *i915,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref)
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{
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intel_display_power_put_unchecked(i915, domain);
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}
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static inline void
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intel_display_power_put_async(struct drm_i915_private *i915,
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enum intel_display_power_domain domain,
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intel_wakeref_t wakeref)
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{
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__intel_display_power_put_async(i915, domain, -1);
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}
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#endif
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void
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intel_display_power_get_in_set(struct drm_i915_private *i915,
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struct intel_display_power_domain_set *power_domain_set,
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enum intel_display_power_domain domain);
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bool
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intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
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struct intel_display_power_domain_set *power_domain_set,
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enum intel_display_power_domain domain);
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void
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intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
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struct intel_display_power_domain_set *power_domain_set,
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struct intel_power_domain_mask *mask);
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static inline void
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intel_display_power_put_all_in_set(struct drm_i915_private *i915,
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struct intel_display_power_domain_set *power_domain_set)
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{
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intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
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}
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void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
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enum intel_display_power_domain
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intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
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enum intel_display_power_domain
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intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
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enum intel_display_power_domain
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intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
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enum intel_display_power_domain
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intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
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enum intel_display_power_domain
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intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
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/*
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* FIXME: We should probably switch this to a 0-based scheme to be consistent
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* with how we now name/number DBUF_CTL instances.
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*/
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enum dbuf_slice {
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DBUF_S1,
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DBUF_S2,
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DBUF_S3,
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DBUF_S4,
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I915_MAX_DBUF_SLICES
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};
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void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
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u8 req_slices);
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#define with_intel_display_power(i915, domain, wf) \
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for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
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intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
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#define with_intel_display_power_if_enabled(i915, domain, wf) \
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for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
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intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
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#endif /* __INTEL_DISPLAY_POWER_H__ */
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