323 lines
9.3 KiB
C
323 lines
9.3 KiB
C
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/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "i915_drv.h"
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#include "i915_vgpu.h"
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#include "intel_gvt.h"
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#include "gem/i915_gem_dmabuf.h"
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#include "gt/intel_context.h"
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#include "gt/intel_ring.h"
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#include "gt/shmem_utils.h"
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/**
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* DOC: Intel GVT-g host support
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*
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* Intel GVT-g is a graphics virtualization technology which shares the
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* GPU among multiple virtual machines on a time-sharing basis. Each
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* virtual machine is presented a virtual GPU (vGPU), which has equivalent
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* features as the underlying physical GPU (pGPU), so i915 driver can run
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* seamlessly in a virtual machine.
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*
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* To virtualize GPU resources GVT-g driver depends on hypervisor technology
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* e.g KVM/VFIO/mdev, Xen, etc. to provide resource access trapping capability
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* and be virtualized within GVT-g device module. More architectural design
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* doc is available on https://01.org/group/2230/documentation-list.
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*/
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static LIST_HEAD(intel_gvt_devices);
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static const struct intel_vgpu_ops *intel_gvt_ops;
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static DEFINE_MUTEX(intel_gvt_mutex);
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static bool is_supported_device(struct drm_i915_private *dev_priv)
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{
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if (IS_BROADWELL(dev_priv))
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return true;
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if (IS_SKYLAKE(dev_priv))
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return true;
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if (IS_KABYLAKE(dev_priv))
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return true;
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if (IS_BROXTON(dev_priv))
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return true;
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if (IS_COFFEELAKE(dev_priv))
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return true;
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if (IS_COMETLAKE(dev_priv))
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return true;
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return false;
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}
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static void free_initial_hw_state(struct drm_i915_private *dev_priv)
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{
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struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;
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vfree(vgpu->initial_mmio);
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vgpu->initial_mmio = NULL;
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kfree(vgpu->initial_cfg_space);
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vgpu->initial_cfg_space = NULL;
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}
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static void save_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
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u32 size)
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{
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struct drm_i915_private *dev_priv = iter->i915;
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u32 *mmio, i;
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for (i = offset; i < offset + size; i += 4) {
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mmio = iter->data + i;
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*mmio = intel_uncore_read_notrace(to_gt(dev_priv)->uncore,
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_MMIO(i));
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}
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}
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static int handle_mmio(struct intel_gvt_mmio_table_iter *iter,
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u32 offset, u32 size)
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{
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if (WARN_ON(!IS_ALIGNED(offset, 4)))
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return -EINVAL;
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save_mmio(iter, offset, size);
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return 0;
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}
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static int save_initial_hw_state(struct drm_i915_private *dev_priv)
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{
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struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
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struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;
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struct intel_gvt_mmio_table_iter iter;
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void *mem;
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int i, ret;
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mem = kzalloc(PCI_CFG_SPACE_EXP_SIZE, GFP_KERNEL);
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if (!mem)
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return -ENOMEM;
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vgpu->initial_cfg_space = mem;
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for (i = 0; i < PCI_CFG_SPACE_EXP_SIZE; i += 4)
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pci_read_config_dword(pdev, i, mem + i);
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mem = vzalloc(2 * SZ_1M);
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if (!mem) {
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ret = -ENOMEM;
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goto err_mmio;
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}
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vgpu->initial_mmio = mem;
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iter.i915 = dev_priv;
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iter.data = vgpu->initial_mmio;
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iter.handle_mmio_cb = handle_mmio;
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ret = intel_gvt_iterate_mmio_table(&iter);
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if (ret)
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goto err_iterate;
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return 0;
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err_iterate:
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vfree(vgpu->initial_mmio);
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vgpu->initial_mmio = NULL;
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err_mmio:
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kfree(vgpu->initial_cfg_space);
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vgpu->initial_cfg_space = NULL;
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return ret;
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}
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static void intel_gvt_init_device(struct drm_i915_private *dev_priv)
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{
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if (!dev_priv->params.enable_gvt) {
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drm_dbg(&dev_priv->drm,
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"GVT-g is disabled by kernel params\n");
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return;
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}
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if (intel_vgpu_active(dev_priv)) {
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drm_info(&dev_priv->drm, "GVT-g is disabled for guest\n");
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return;
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}
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if (!is_supported_device(dev_priv)) {
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drm_info(&dev_priv->drm,
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"Unsupported device. GVT-g is disabled\n");
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return;
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}
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if (intel_uc_wants_guc_submission(&to_gt(dev_priv)->uc)) {
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drm_err(&dev_priv->drm,
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"Graphics virtualization is not yet supported with GuC submission\n");
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return;
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}
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if (save_initial_hw_state(dev_priv)) {
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drm_dbg(&dev_priv->drm, "Failed to save initial HW state\n");
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return;
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}
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if (intel_gvt_ops->init_device(dev_priv))
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drm_dbg(&dev_priv->drm, "Fail to init GVT device\n");
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}
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static void intel_gvt_clean_device(struct drm_i915_private *dev_priv)
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{
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if (dev_priv->gvt)
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intel_gvt_ops->clean_device(dev_priv);
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free_initial_hw_state(dev_priv);
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}
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int intel_gvt_set_ops(const struct intel_vgpu_ops *ops)
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{
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struct drm_i915_private *dev_priv;
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mutex_lock(&intel_gvt_mutex);
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if (intel_gvt_ops) {
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mutex_unlock(&intel_gvt_mutex);
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return -EINVAL;
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}
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intel_gvt_ops = ops;
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list_for_each_entry(dev_priv, &intel_gvt_devices, vgpu.entry)
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intel_gvt_init_device(dev_priv);
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mutex_unlock(&intel_gvt_mutex);
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(intel_gvt_set_ops, I915_GVT);
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void intel_gvt_clear_ops(const struct intel_vgpu_ops *ops)
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{
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struct drm_i915_private *dev_priv;
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mutex_lock(&intel_gvt_mutex);
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if (intel_gvt_ops != ops) {
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mutex_unlock(&intel_gvt_mutex);
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return;
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}
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list_for_each_entry(dev_priv, &intel_gvt_devices, vgpu.entry)
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intel_gvt_clean_device(dev_priv);
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intel_gvt_ops = NULL;
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mutex_unlock(&intel_gvt_mutex);
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}
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EXPORT_SYMBOL_NS_GPL(intel_gvt_clear_ops, I915_GVT);
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/**
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* intel_gvt_init - initialize GVT components
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* @dev_priv: drm i915 private data
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*
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* This function is called at the initialization stage to create a GVT device.
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*
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* Returns:
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* Zero on success, negative error code if failed.
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*
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*/
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int intel_gvt_init(struct drm_i915_private *dev_priv)
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{
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if (i915_inject_probe_failure(dev_priv))
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return -ENODEV;
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mutex_lock(&intel_gvt_mutex);
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list_add_tail(&dev_priv->vgpu.entry, &intel_gvt_devices);
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if (intel_gvt_ops)
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intel_gvt_init_device(dev_priv);
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mutex_unlock(&intel_gvt_mutex);
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return 0;
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}
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/**
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* intel_gvt_driver_remove - cleanup GVT components when i915 driver is
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* unbinding
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* @dev_priv: drm i915 private *
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*
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* This function is called at the i915 driver unloading stage, to shutdown
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* GVT components and release the related resources.
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*/
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void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)
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{
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mutex_lock(&intel_gvt_mutex);
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intel_gvt_clean_device(dev_priv);
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list_del(&dev_priv->vgpu.entry);
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mutex_unlock(&intel_gvt_mutex);
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}
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/**
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* intel_gvt_resume - GVT resume routine wapper
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*
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* @dev_priv: drm i915 private *
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*
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* This function is called at the i915 driver resume stage to restore required
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* HW status for GVT so that vGPU can continue running after resumed.
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*/
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void intel_gvt_resume(struct drm_i915_private *dev_priv)
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{
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mutex_lock(&intel_gvt_mutex);
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if (dev_priv->gvt)
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intel_gvt_ops->pm_resume(dev_priv);
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mutex_unlock(&intel_gvt_mutex);
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}
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/*
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* Exported here so that the exports only get created when GVT support is
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* actually enabled.
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*/
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EXPORT_SYMBOL_NS_GPL(i915_gem_object_alloc, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_object_create_shmem, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_object_init, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_object_ggtt_pin_ww, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_object_pin_map, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_object_set_to_cpu_domain, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(__i915_gem_object_flush_map, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(__i915_gem_object_set_pages, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_gtt_insert, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_prime_export, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_ww_ctx_init, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_ww_ctx_backoff, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_gem_ww_ctx_fini, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_ppgtt_create, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_request_add, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_request_create, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_request_wait, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_reserve_fence, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_unreserve_fence, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_vm_release, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(_i915_vma_move_to_active, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(intel_context_create, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(__intel_context_do_pin, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(__intel_context_do_unpin, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(intel_ring_begin, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(intel_runtime_pm_get, I915_GVT);
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
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EXPORT_SYMBOL_NS_GPL(intel_runtime_pm_put, I915_GVT);
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#endif
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EXPORT_SYMBOL_NS_GPL(intel_runtime_pm_put_unchecked, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(intel_uncore_forcewake_for_reg, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(intel_uncore_forcewake_get, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(intel_uncore_forcewake_put, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(shmem_pin_map, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(shmem_unpin_map, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(__px_dma, I915_GVT);
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EXPORT_SYMBOL_NS_GPL(i915_fence_ops, I915_GVT);
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