249 lines
6.8 KiB
C
249 lines
6.8 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2013-2021 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_pcode.h"
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static int gen6_check_mailbox_status(u32 mbox)
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{
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switch (mbox & GEN6_PCODE_ERROR_MASK) {
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case GEN6_PCODE_SUCCESS:
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return 0;
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case GEN6_PCODE_UNIMPLEMENTED_CMD:
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return -ENODEV;
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case GEN6_PCODE_ILLEGAL_CMD:
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return -ENXIO;
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case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
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case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
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return -EOVERFLOW;
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case GEN6_PCODE_TIMEOUT:
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return -ETIMEDOUT;
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default:
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MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
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return 0;
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}
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}
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static int gen7_check_mailbox_status(u32 mbox)
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{
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switch (mbox & GEN6_PCODE_ERROR_MASK) {
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case GEN6_PCODE_SUCCESS:
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return 0;
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case GEN6_PCODE_ILLEGAL_CMD:
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return -ENXIO;
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case GEN7_PCODE_TIMEOUT:
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return -ETIMEDOUT;
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case GEN7_PCODE_ILLEGAL_DATA:
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return -EINVAL;
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case GEN11_PCODE_ILLEGAL_SUBCOMMAND:
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return -ENXIO;
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case GEN11_PCODE_LOCKED:
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return -EBUSY;
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case GEN11_PCODE_REJECTED:
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return -EACCES;
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case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
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return -EOVERFLOW;
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default:
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MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
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return 0;
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}
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}
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static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
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u32 *val, u32 *val1,
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int fast_timeout_us, int slow_timeout_ms,
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bool is_read)
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{
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lockdep_assert_held(&uncore->i915->sb_lock);
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/*
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* GEN6_PCODE_* are outside of the forcewake domain, we can use
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* intel_uncore_read/write_fw variants to reduce the amount of work
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* required when reading/writing.
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*/
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if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
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return -EAGAIN;
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intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
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intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
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intel_uncore_write_fw(uncore,
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GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
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if (__intel_wait_for_register_fw(uncore,
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GEN6_PCODE_MAILBOX,
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GEN6_PCODE_READY, 0,
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fast_timeout_us,
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slow_timeout_ms,
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&mbox))
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return -ETIMEDOUT;
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if (is_read)
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*val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
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if (is_read && val1)
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*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
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if (GRAPHICS_VER(uncore->i915) > 6)
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return gen7_check_mailbox_status(mbox);
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else
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return gen6_check_mailbox_status(mbox);
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}
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int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
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{
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int err;
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mutex_lock(&uncore->i915->sb_lock);
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err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true);
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mutex_unlock(&uncore->i915->sb_lock);
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if (err) {
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drm_dbg(&uncore->i915->drm,
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"warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
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mbox, __builtin_return_address(0), err);
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}
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return err;
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}
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int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
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int fast_timeout_us, int slow_timeout_ms)
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{
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int err;
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mutex_lock(&uncore->i915->sb_lock);
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err = __snb_pcode_rw(uncore, mbox, &val, NULL,
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fast_timeout_us, slow_timeout_ms, false);
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mutex_unlock(&uncore->i915->sb_lock);
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if (err) {
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drm_dbg(&uncore->i915->drm,
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"warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
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val, mbox, __builtin_return_address(0), err);
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}
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return err;
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}
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static bool skl_pcode_try_request(struct intel_uncore *uncore, u32 mbox,
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u32 request, u32 reply_mask, u32 reply,
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u32 *status)
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{
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*status = __snb_pcode_rw(uncore, mbox, &request, NULL, 500, 0, true);
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return (*status == 0) && ((request & reply_mask) == reply);
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}
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/**
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* skl_pcode_request - send PCODE request until acknowledgment
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* @uncore: uncore
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* @mbox: PCODE mailbox ID the request is targeted for
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* @request: request ID
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* @reply_mask: mask used to check for request acknowledgment
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* @reply: value used to check for request acknowledgment
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* @timeout_base_ms: timeout for polling with preemption enabled
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*
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* Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
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* reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
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* The request is acknowledged once the PCODE reply dword equals @reply after
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* applying @reply_mask. Polling is first attempted with preemption enabled
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* for @timeout_base_ms and if this times out for another 50 ms with
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* preemption disabled.
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*
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* Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
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* other error as reported by PCODE.
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*/
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int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
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u32 reply_mask, u32 reply, int timeout_base_ms)
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{
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u32 status;
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int ret;
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mutex_lock(&uncore->i915->sb_lock);
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#define COND \
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skl_pcode_try_request(uncore, mbox, request, reply_mask, reply, &status)
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/*
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* Prime the PCODE by doing a request first. Normally it guarantees
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* that a subsequent request, at most @timeout_base_ms later, succeeds.
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* _wait_for() doesn't guarantee when its passed condition is evaluated
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* first, so send the first request explicitly.
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*/
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if (COND) {
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ret = 0;
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goto out;
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}
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ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
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if (!ret)
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goto out;
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/*
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* The above can time out if the number of requests was low (2 in the
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* worst case) _and_ PCODE was busy for some reason even after a
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* (queued) request and @timeout_base_ms delay. As a workaround retry
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* the poll with preemption disabled to maximize the number of
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* requests. Increase the timeout from @timeout_base_ms to 50ms to
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* account for interrupts that could reduce the number of these
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* requests, and for any quirks of the PCODE firmware that delays
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* the request completion.
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*/
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drm_dbg_kms(&uncore->i915->drm,
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"PCODE timeout, retrying with preemption disabled\n");
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drm_WARN_ON_ONCE(&uncore->i915->drm, timeout_base_ms > 3);
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preempt_disable();
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ret = wait_for_atomic(COND, 50);
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preempt_enable();
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out:
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mutex_unlock(&uncore->i915->sb_lock);
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return status ? status : ret;
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#undef COND
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}
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int intel_pcode_init(struct intel_uncore *uncore)
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{
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if (!IS_DGFX(uncore->i915))
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return 0;
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return skl_pcode_request(uncore, DG1_PCODE_STATUS,
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DG1_UNCORE_GET_INIT_STATUS,
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DG1_UNCORE_INIT_STATUS_COMPLETE,
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DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
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}
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int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)
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{
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intel_wakeref_t wakeref;
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u32 mbox;
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int err;
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mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
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| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
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| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
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with_intel_runtime_pm(uncore->rpm, wakeref)
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err = snb_pcode_read(uncore, mbox, val, NULL);
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return err;
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}
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int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)
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{
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intel_wakeref_t wakeref;
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u32 mbox;
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int err;
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mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
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| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
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| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
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with_intel_runtime_pm(uncore->rpm, wakeref)
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err = snb_pcode_write(uncore, mbox, val);
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return err;
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}
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