400 lines
11 KiB
C
400 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#include <drm/drm_fourcc.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include "mtk_disp_drv.h"
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#include "mtk_drm_crtc.h"
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_drv.h"
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#define DISP_REG_RDMA_INT_ENABLE 0x0000
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#define DISP_REG_RDMA_INT_STATUS 0x0004
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#define RDMA_TARGET_LINE_INT BIT(5)
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#define RDMA_FIFO_UNDERFLOW_INT BIT(4)
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#define RDMA_EOF_ABNORMAL_INT BIT(3)
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#define RDMA_FRAME_END_INT BIT(2)
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#define RDMA_FRAME_START_INT BIT(1)
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#define RDMA_REG_UPDATE_INT BIT(0)
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#define DISP_REG_RDMA_GLOBAL_CON 0x0010
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#define RDMA_ENGINE_EN BIT(0)
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#define RDMA_MODE_MEMORY BIT(1)
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#define DISP_REG_RDMA_SIZE_CON_0 0x0014
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#define RDMA_MATRIX_ENABLE BIT(17)
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#define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20)
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#define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20)
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#define DISP_REG_RDMA_SIZE_CON_1 0x0018
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#define DISP_REG_RDMA_TARGET_LINE 0x001c
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#define DISP_RDMA_MEM_CON 0x0024
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#define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4)
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#define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
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#define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4)
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#define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4)
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#define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
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#define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
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#define MEM_MODE_INPUT_SWAP BIT(8)
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#define DISP_RDMA_MEM_SRC_PITCH 0x002c
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#define DISP_RDMA_MEM_GMC_SETTING_0 0x0030
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#define DISP_REG_RDMA_FIFO_CON 0x0040
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#define RDMA_FIFO_UNDERFLOW_EN BIT(31)
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#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
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#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
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#define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
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#define DISP_RDMA_MEM_START_ADDR 0x0f00
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#define RDMA_MEM_GMC 0x40402020
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struct mtk_disp_rdma_data {
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unsigned int fifo_size;
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};
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/*
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* struct mtk_disp_rdma - DISP_RDMA driver structure
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* @data: local driver data
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*/
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struct mtk_disp_rdma {
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struct clk *clk;
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void __iomem *regs;
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struct cmdq_client_reg cmdq_reg;
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const struct mtk_disp_rdma_data *data;
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void (*vblank_cb)(void *data);
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void *vblank_cb_data;
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u32 fifo_size;
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};
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static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
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{
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struct mtk_disp_rdma *priv = dev_id;
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/* Clear frame completion interrupt */
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writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
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if (!priv->vblank_cb)
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return IRQ_NONE;
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priv->vblank_cb(priv->vblank_cb_data);
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return IRQ_HANDLED;
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}
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static void rdma_update_bits(struct device *dev, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
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unsigned int tmp = readl(rdma->regs + reg);
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tmp = (tmp & ~mask) | (val & mask);
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writel(tmp, rdma->regs + reg);
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}
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void mtk_rdma_register_vblank_cb(struct device *dev,
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void (*vblank_cb)(void *),
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void *vblank_cb_data)
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{
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struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
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rdma->vblank_cb = vblank_cb;
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rdma->vblank_cb_data = vblank_cb_data;
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}
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void mtk_rdma_unregister_vblank_cb(struct device *dev)
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{
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struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
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rdma->vblank_cb = NULL;
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rdma->vblank_cb_data = NULL;
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}
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void mtk_rdma_enable_vblank(struct device *dev)
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{
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rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
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RDMA_FRAME_END_INT);
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}
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void mtk_rdma_disable_vblank(struct device *dev)
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{
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rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
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}
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int mtk_rdma_clk_enable(struct device *dev)
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{
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struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
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return clk_prepare_enable(rdma->clk);
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}
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void mtk_rdma_clk_disable(struct device *dev)
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{
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struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
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clk_disable_unprepare(rdma->clk);
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}
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void mtk_rdma_start(struct device *dev)
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{
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rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
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RDMA_ENGINE_EN);
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}
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void mtk_rdma_stop(struct device *dev)
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{
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rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
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}
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void mtk_rdma_config(struct device *dev, unsigned int width,
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unsigned int height, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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{
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unsigned int threshold;
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unsigned int reg;
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struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
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u32 rdma_fifo_size;
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mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,
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DISP_REG_RDMA_SIZE_CON_0, 0xfff);
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mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,
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DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
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if (rdma->fifo_size)
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rdma_fifo_size = rdma->fifo_size;
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else
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rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
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/*
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* Enable FIFO underflow since DSI and DPI can't be blocked.
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* Keep the FIFO pseudo size reset default of 8 KiB. Set the
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* output threshold to 70% of max fifo size to make sure the
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* threhold will not overflow
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*/
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threshold = rdma_fifo_size * 7 / 10;
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reg = RDMA_FIFO_UNDERFLOW_EN |
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RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
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RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
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mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);
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}
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static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
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unsigned int fmt)
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{
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/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
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* is defined in mediatek HW data sheet.
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* The alphabet order in XXX is no relation to data
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* arrangement in memory.
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*/
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switch (fmt) {
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default:
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case DRM_FORMAT_RGB565:
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return MEM_MODE_INPUT_FORMAT_RGB565;
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case DRM_FORMAT_BGR565:
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return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
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case DRM_FORMAT_RGB888:
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return MEM_MODE_INPUT_FORMAT_RGB888;
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case DRM_FORMAT_BGR888:
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return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
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case DRM_FORMAT_RGBX8888:
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case DRM_FORMAT_RGBA8888:
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return MEM_MODE_INPUT_FORMAT_ARGB8888;
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case DRM_FORMAT_BGRX8888:
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case DRM_FORMAT_BGRA8888:
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return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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return MEM_MODE_INPUT_FORMAT_RGBA8888;
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
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case DRM_FORMAT_UYVY:
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return MEM_MODE_INPUT_FORMAT_UYVY;
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case DRM_FORMAT_YUYV:
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return MEM_MODE_INPUT_FORMAT_YUYV;
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}
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}
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unsigned int mtk_rdma_layer_nr(struct device *dev)
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{
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return 1;
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}
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void mtk_rdma_layer_config(struct device *dev, unsigned int idx,
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struct mtk_plane_state *state,
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struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
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struct mtk_plane_pending_state *pending = &state->pending;
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unsigned int addr = pending->addr;
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unsigned int pitch = pending->pitch & 0xffff;
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unsigned int fmt = pending->format;
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unsigned int con;
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con = rdma_fmt_convert(rdma, fmt);
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mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);
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if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
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mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,
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DISP_REG_RDMA_SIZE_CON_0,
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RDMA_MATRIX_ENABLE);
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mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
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&rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0,
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RDMA_MATRIX_INT_MTX_SEL);
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} else {
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mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,
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DISP_REG_RDMA_SIZE_CON_0,
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RDMA_MATRIX_ENABLE);
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}
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mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,
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DISP_RDMA_MEM_START_ADDR);
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mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,
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DISP_RDMA_MEM_SRC_PITCH);
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mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,
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DISP_RDMA_MEM_GMC_SETTING_0);
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mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,
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DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
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}
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static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
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void *data)
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{
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return 0;
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}
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static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
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void *data)
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{
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}
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static const struct component_ops mtk_disp_rdma_component_ops = {
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.bind = mtk_disp_rdma_bind,
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.unbind = mtk_disp_rdma_unbind,
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};
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static int mtk_disp_rdma_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_disp_rdma *priv;
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struct resource *res;
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int irq;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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dev_err(dev, "failed to get rdma clk\n");
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return PTR_ERR(priv->clk);
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->regs)) {
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dev_err(dev, "failed to ioremap rdma\n");
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return PTR_ERR(priv->regs);
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}
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
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if (ret)
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dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
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#endif
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if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) {
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ret = of_property_read_u32(dev->of_node,
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"mediatek,rdma-fifo-size",
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&priv->fifo_size);
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if (ret) {
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dev_err(dev, "Failed to get rdma fifo size\n");
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return ret;
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}
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}
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/* Disable and clear pending interrupts */
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writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE);
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writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
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ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
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IRQF_TRIGGER_NONE, dev_name(dev), priv);
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if (ret < 0) {
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dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
priv->data = of_device_get_match_data(dev);
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, priv);
|
||
|
|
|
||
|
|
pm_runtime_enable(dev);
|
||
|
|
|
||
|
|
ret = component_add(dev, &mtk_disp_rdma_component_ops);
|
||
|
|
if (ret) {
|
||
|
|
pm_runtime_disable(dev);
|
||
|
|
dev_err(dev, "Failed to add component: %d\n", ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mtk_disp_rdma_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
|
||
|
|
|
||
|
|
pm_runtime_disable(&pdev->dev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
|
||
|
|
.fifo_size = SZ_4K,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
|
||
|
|
.fifo_size = SZ_8K,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
|
||
|
|
.fifo_size = 5 * SZ_1K,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
|
||
|
|
.fifo_size = 1920,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
|
||
|
|
{ .compatible = "mediatek,mt2701-disp-rdma",
|
||
|
|
.data = &mt2701_rdma_driver_data},
|
||
|
|
{ .compatible = "mediatek,mt8173-disp-rdma",
|
||
|
|
.data = &mt8173_rdma_driver_data},
|
||
|
|
{ .compatible = "mediatek,mt8183-disp-rdma",
|
||
|
|
.data = &mt8183_rdma_driver_data},
|
||
|
|
{ .compatible = "mediatek,mt8195-disp-rdma",
|
||
|
|
.data = &mt8195_rdma_driver_data},
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
|
||
|
|
|
||
|
|
struct platform_driver mtk_disp_rdma_driver = {
|
||
|
|
.probe = mtk_disp_rdma_probe,
|
||
|
|
.remove = mtk_disp_rdma_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "mediatek-disp-rdma",
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.of_match_table = mtk_disp_rdma_driver_dt_match,
|
||
|
|
},
|
||
|
|
};
|