559 lines
15 KiB
C
559 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_gem_atomic_helper.h>
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#include <drm/drm_probe_helper.h>
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#include "mgag200_drv.h"
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static int mgag200_g200se_init_pci_options(struct pci_dev *pdev)
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{
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struct device *dev = &pdev->dev;
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bool has_sgram;
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u32 option;
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int err;
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err = pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
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if (err != PCIBIOS_SUCCESSFUL) {
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dev_err(dev, "pci_read_config_dword(PCI_MGA_OPTION) failed: %d\n", err);
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return pcibios_err_to_errno(err);
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}
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has_sgram = !!(option & PCI_MGA_OPTION_HARDPWMSK);
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option = 0x40049120;
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if (has_sgram)
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option |= PCI_MGA_OPTION_HARDPWMSK;
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return mgag200_init_pci_options(pdev, option, 0x00008000);
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}
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static void mgag200_g200se_init_registers(struct mgag200_g200se_device *g200se)
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{
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static const u8 dacvalue[] = {
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MGAG200_DAC_DEFAULT(0x03,
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MGA1064_PIX_CLK_CTL_SEL_PLL,
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MGA1064_MISC_CTL_DAC_EN |
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MGA1064_MISC_CTL_VGA8 |
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MGA1064_MISC_CTL_DAC_RAM_CS,
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0x00, 0x00, 0x00)
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};
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struct mga_device *mdev = &g200se->base;
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size_t i;
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for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
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if ((i <= 0x17) ||
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(i == 0x1b) ||
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(i == 0x1c) ||
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((i >= 0x1f) && (i <= 0x29)) ||
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((i == 0x2c) || (i == 0x2d) || (i == 0x2e)) ||
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((i >= 0x30) && (i <= 0x37)))
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continue;
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WREG_DAC(i, dacvalue[i]);
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}
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mgag200_init_registers(mdev);
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}
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static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev,
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const struct drm_display_mode *mode,
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const struct drm_format_info *format)
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{
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struct mgag200_g200se_device *g200se = to_mgag200_g200se_device(&mdev->base);
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unsigned int hiprilvl;
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u8 crtcext6;
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if (g200se->unique_rev_id >= 0x04) {
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hiprilvl = 0;
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} else if (g200se->unique_rev_id >= 0x02) {
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unsigned int bpp;
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unsigned long mb;
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if (format->cpp[0] * 8 > 16)
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bpp = 32;
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else if (format->cpp[0] * 8 > 8)
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bpp = 16;
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else
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bpp = 8;
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mb = (mode->clock * bpp) / 1000;
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if (mb > 3100)
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hiprilvl = 0;
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else if (mb > 2600)
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hiprilvl = 1;
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else if (mb > 1900)
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hiprilvl = 2;
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else if (mb > 1160)
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hiprilvl = 3;
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else if (mb > 440)
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hiprilvl = 4;
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else
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hiprilvl = 5;
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} else if (g200se->unique_rev_id >= 0x01) {
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hiprilvl = 3;
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} else {
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hiprilvl = 4;
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}
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crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */
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WREG_ECRT(0x06, crtcext6);
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}
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/*
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* PIXPLLC
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*/
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static int mgag200_g200se_00_pixpllc_atomic_check(struct drm_crtc *crtc,
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struct drm_atomic_state *new_state)
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{
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static const unsigned int vcomax = 320000;
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static const unsigned int vcomin = 160000;
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static const unsigned int pllreffreq = 25000;
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struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc);
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struct mgag200_crtc_state *new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state);
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long clock = new_crtc_state->mode.clock;
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struct mgag200_pll_values *pixpllc = &new_mgag200_crtc_state->pixpllc;
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unsigned int delta, tmpdelta, permitteddelta;
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unsigned int testp, testm, testn;
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unsigned int p, m, n, s;
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unsigned int computed;
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m = n = p = s = 0;
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delta = 0xffffffff;
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permitteddelta = clock * 5 / 1000;
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for (testp = 8; testp > 0; testp /= 2) {
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if (clock * testp > vcomax)
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continue;
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if (clock * testp < vcomin)
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continue;
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for (testn = 17; testn < 256; testn++) {
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for (testm = 1; testm < 32; testm++) {
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computed = (pllreffreq * testn) / (testm * testp);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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m = testm;
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n = testn;
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p = testp;
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}
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}
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}
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}
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if (delta > permitteddelta) {
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pr_warn("PLL delta too large\n");
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return -EINVAL;
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}
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pixpllc->m = m;
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pixpllc->n = n;
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pixpllc->p = p;
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pixpllc->s = s;
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return 0;
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}
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static void mgag200_g200se_00_pixpllc_atomic_update(struct drm_crtc *crtc,
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struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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struct drm_crtc_state *crtc_state = crtc->state;
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struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
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struct mgag200_pll_values *pixpllc = &mgag200_crtc_state->pixpllc;
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unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
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u8 xpixpllcm, xpixpllcn, xpixpllcp;
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pixpllcm = pixpllc->m - 1;
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pixpllcn = pixpllc->n - 1;
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pixpllcp = pixpllc->p - 1;
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pixpllcs = pixpllc->s;
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xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1);
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xpixpllcn = pixpllcn;
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xpixpllcp = (pixpllcs << 3) | pixpllcp;
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WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
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WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
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WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
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WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
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}
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static int mgag200_g200se_04_pixpllc_atomic_check(struct drm_crtc *crtc,
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struct drm_atomic_state *new_state)
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{
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static const unsigned int vcomax = 1600000;
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static const unsigned int vcomin = 800000;
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static const unsigned int pllreffreq = 25000;
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static const unsigned int pvalues_e4[] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
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struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc);
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struct mgag200_crtc_state *new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state);
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long clock = new_crtc_state->mode.clock;
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struct mgag200_pll_values *pixpllc = &new_mgag200_crtc_state->pixpllc;
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unsigned int delta, tmpdelta, permitteddelta;
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unsigned int testp, testm, testn;
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unsigned int p, m, n, s;
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unsigned int computed;
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unsigned int fvv;
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unsigned int i;
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m = n = p = s = 0;
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delta = 0xffffffff;
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if (clock < 25000)
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clock = 25000;
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clock = clock * 2;
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/* Permited delta is 0.5% as VESA Specification */
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permitteddelta = clock * 5 / 1000;
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for (i = 0 ; i < ARRAY_SIZE(pvalues_e4); i++) {
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testp = pvalues_e4[i];
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if ((clock * testp) > vcomax)
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continue;
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if ((clock * testp) < vcomin)
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continue;
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for (testn = 50; testn <= 256; testn++) {
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for (testm = 1; testm <= 32; testm++) {
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computed = (pllreffreq * testn) / (testm * testp);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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m = testm;
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n = testn;
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p = testp;
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}
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}
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}
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}
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fvv = pllreffreq * n / m;
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fvv = (fvv - 800000) / 50000;
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if (fvv > 15)
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fvv = 15;
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s = fvv << 1;
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if (delta > permitteddelta) {
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pr_warn("PLL delta too large\n");
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return -EINVAL;
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}
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pixpllc->m = m;
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pixpllc->n = n;
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pixpllc->p = p;
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pixpllc->s = s;
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return 0;
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}
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static void mgag200_g200se_04_pixpllc_atomic_update(struct drm_crtc *crtc,
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struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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struct drm_crtc_state *crtc_state = crtc->state;
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struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
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struct mgag200_pll_values *pixpllc = &mgag200_crtc_state->pixpllc;
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unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
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u8 xpixpllcm, xpixpllcn, xpixpllcp;
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pixpllcm = pixpllc->m - 1;
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pixpllcn = pixpllc->n - 1;
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pixpllcp = pixpllc->p - 1;
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pixpllcs = pixpllc->s;
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// For G200SE A, BIT(7) should be set unconditionally.
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xpixpllcm = BIT(7) | pixpllcm;
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xpixpllcn = pixpllcn;
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xpixpllcp = (pixpllcs << 3) | pixpllcp;
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WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
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WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
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WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
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WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
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WREG_DAC(0x1a, 0x09);
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msleep(20);
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WREG_DAC(0x1a, 0x01);
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}
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/*
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* Mode-setting pipeline
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*/
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static const struct drm_plane_helper_funcs mgag200_g200se_primary_plane_helper_funcs = {
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MGAG200_PRIMARY_PLANE_HELPER_FUNCS,
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};
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static const struct drm_plane_funcs mgag200_g200se_primary_plane_funcs = {
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MGAG200_PRIMARY_PLANE_FUNCS,
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};
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static void mgag200_g200se_crtc_helper_atomic_enable(struct drm_crtc *crtc,
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struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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const struct mgag200_device_funcs *funcs = mdev->funcs;
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struct drm_crtc_state *crtc_state = crtc->state;
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struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
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struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
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const struct drm_format_info *format = mgag200_crtc_state->format;
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if (funcs->disable_vidrst)
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funcs->disable_vidrst(mdev);
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mgag200_set_format_regs(mdev, format);
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mgag200_set_mode_regs(mdev, adjusted_mode);
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if (funcs->pixpllc_atomic_update)
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funcs->pixpllc_atomic_update(crtc, old_state);
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mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, format);
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mgag200_enable_display(mdev);
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if (funcs->enable_vidrst)
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funcs->enable_vidrst(mdev);
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}
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static const struct drm_crtc_helper_funcs mgag200_g200se_crtc_helper_funcs = {
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.mode_valid = mgag200_crtc_helper_mode_valid,
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.atomic_check = mgag200_crtc_helper_atomic_check,
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.atomic_flush = mgag200_crtc_helper_atomic_flush,
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.atomic_enable = mgag200_g200se_crtc_helper_atomic_enable,
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.atomic_disable = mgag200_crtc_helper_atomic_disable
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};
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static const struct drm_crtc_funcs mgag200_g200se_crtc_funcs = {
|
||
|
|
MGAG200_CRTC_FUNCS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct drm_encoder_funcs mgag200_g200se_dac_encoder_funcs = {
|
||
|
|
MGAG200_DAC_ENCODER_FUNCS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct drm_connector_helper_funcs mgag200_g200se_vga_connector_helper_funcs = {
|
||
|
|
MGAG200_VGA_CONNECTOR_HELPER_FUNCS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct drm_connector_funcs mgag200_g200se_vga_connector_funcs = {
|
||
|
|
MGAG200_VGA_CONNECTOR_FUNCS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int mgag200_g200se_pipeline_init(struct mga_device *mdev)
|
||
|
|
{
|
||
|
|
struct drm_device *dev = &mdev->base;
|
||
|
|
struct drm_plane *primary_plane = &mdev->primary_plane;
|
||
|
|
struct drm_crtc *crtc = &mdev->crtc;
|
||
|
|
struct drm_encoder *encoder = &mdev->encoder;
|
||
|
|
struct mga_i2c_chan *i2c = &mdev->i2c;
|
||
|
|
struct drm_connector *connector = &mdev->connector;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = drm_universal_plane_init(dev, primary_plane, 0,
|
||
|
|
&mgag200_g200se_primary_plane_funcs,
|
||
|
|
mgag200_primary_plane_formats,
|
||
|
|
mgag200_primary_plane_formats_size,
|
||
|
|
mgag200_primary_plane_fmtmods,
|
||
|
|
DRM_PLANE_TYPE_PRIMARY, NULL);
|
||
|
|
if (ret) {
|
||
|
|
drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
drm_plane_helper_add(primary_plane, &mgag200_g200se_primary_plane_helper_funcs);
|
||
|
|
drm_plane_enable_fb_damage_clips(primary_plane);
|
||
|
|
|
||
|
|
ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL,
|
||
|
|
&mgag200_g200se_crtc_funcs, NULL);
|
||
|
|
if (ret) {
|
||
|
|
drm_err(dev, "drm_crtc_init_with_planes() failed: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
drm_crtc_helper_add(crtc, &mgag200_g200se_crtc_helper_funcs);
|
||
|
|
|
||
|
|
/* FIXME: legacy gamma tables, but atomic gamma doesn't work without */
|
||
|
|
drm_mode_crtc_set_gamma_size(crtc, MGAG200_LUT_SIZE);
|
||
|
|
drm_crtc_enable_color_mgmt(crtc, 0, false, MGAG200_LUT_SIZE);
|
||
|
|
|
||
|
|
encoder->possible_crtcs = drm_crtc_mask(crtc);
|
||
|
|
ret = drm_encoder_init(dev, encoder, &mgag200_g200se_dac_encoder_funcs,
|
||
|
|
DRM_MODE_ENCODER_DAC, NULL);
|
||
|
|
if (ret) {
|
||
|
|
drm_err(dev, "drm_encoder_init() failed: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = mgag200_i2c_init(mdev, i2c);
|
||
|
|
if (ret) {
|
||
|
|
drm_err(dev, "failed to add DDC bus: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = drm_connector_init_with_ddc(dev, connector,
|
||
|
|
&mgag200_g200se_vga_connector_funcs,
|
||
|
|
DRM_MODE_CONNECTOR_VGA,
|
||
|
|
&i2c->adapter);
|
||
|
|
if (ret) {
|
||
|
|
drm_err(dev, "drm_connector_init_with_ddc() failed: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
drm_connector_helper_add(connector, &mgag200_g200se_vga_connector_helper_funcs);
|
||
|
|
|
||
|
|
ret = drm_connector_attach_encoder(connector, encoder);
|
||
|
|
if (ret) {
|
||
|
|
drm_err(dev, "drm_connector_attach_encoder() failed: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* DRM device
|
||
|
|
*/
|
||
|
|
|
||
|
|
static const struct mgag200_device_info mgag200_g200se_a_01_device_info =
|
||
|
|
MGAG200_DEVICE_INFO_INIT(1600, 1200, 24400, false, 0, 1, true);
|
||
|
|
|
||
|
|
static const struct mgag200_device_info mgag200_g200se_a_02_device_info =
|
||
|
|
MGAG200_DEVICE_INFO_INIT(1920, 1200, 30100, false, 0, 1, true);
|
||
|
|
|
||
|
|
static const struct mgag200_device_info mgag200_g200se_a_03_device_info =
|
||
|
|
MGAG200_DEVICE_INFO_INIT(2048, 2048, 55000, false, 0, 1, false);
|
||
|
|
|
||
|
|
static const struct mgag200_device_info mgag200_g200se_b_01_device_info =
|
||
|
|
MGAG200_DEVICE_INFO_INIT(1600, 1200, 24400, false, 0, 1, false);
|
||
|
|
|
||
|
|
static const struct mgag200_device_info mgag200_g200se_b_02_device_info =
|
||
|
|
MGAG200_DEVICE_INFO_INIT(1920, 1200, 30100, false, 0, 1, false);
|
||
|
|
|
||
|
|
static const struct mgag200_device_info mgag200_g200se_b_03_device_info =
|
||
|
|
MGAG200_DEVICE_INFO_INIT(2048, 2048, 55000, false, 0, 1, false);
|
||
|
|
|
||
|
|
static int mgag200_g200se_init_unique_rev_id(struct mgag200_g200se_device *g200se)
|
||
|
|
{
|
||
|
|
struct mga_device *mdev = &g200se->base;
|
||
|
|
struct drm_device *dev = &mdev->base;
|
||
|
|
|
||
|
|
/* stash G200 SE model number for later use */
|
||
|
|
g200se->unique_rev_id = RREG32(0x1e24);
|
||
|
|
if (!g200se->unique_rev_id)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
drm_dbg(dev, "G200 SE unique revision id is 0x%x\n", g200se->unique_rev_id);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct mgag200_device_funcs mgag200_g200se_00_device_funcs = {
|
||
|
|
.pixpllc_atomic_check = mgag200_g200se_00_pixpllc_atomic_check,
|
||
|
|
.pixpllc_atomic_update = mgag200_g200se_00_pixpllc_atomic_update,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct mgag200_device_funcs mgag200_g200se_04_device_funcs = {
|
||
|
|
.pixpllc_atomic_check = mgag200_g200se_04_pixpllc_atomic_check,
|
||
|
|
.pixpllc_atomic_update = mgag200_g200se_04_pixpllc_atomic_update,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv,
|
||
|
|
enum mga_type type)
|
||
|
|
{
|
||
|
|
struct mgag200_g200se_device *g200se;
|
||
|
|
const struct mgag200_device_info *info;
|
||
|
|
const struct mgag200_device_funcs *funcs;
|
||
|
|
struct mga_device *mdev;
|
||
|
|
struct drm_device *dev;
|
||
|
|
resource_size_t vram_available;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
g200se = devm_drm_dev_alloc(&pdev->dev, drv, struct mgag200_g200se_device, base.base);
|
||
|
|
if (IS_ERR(g200se))
|
||
|
|
return ERR_CAST(g200se);
|
||
|
|
mdev = &g200se->base;
|
||
|
|
dev = &mdev->base;
|
||
|
|
|
||
|
|
pci_set_drvdata(pdev, dev);
|
||
|
|
|
||
|
|
ret = mgag200_g200se_init_pci_options(pdev);
|
||
|
|
if (ret)
|
||
|
|
return ERR_PTR(ret);
|
||
|
|
|
||
|
|
ret = mgag200_device_preinit(mdev);
|
||
|
|
if (ret)
|
||
|
|
return ERR_PTR(ret);
|
||
|
|
|
||
|
|
ret = mgag200_g200se_init_unique_rev_id(g200se);
|
||
|
|
if (ret)
|
||
|
|
return ERR_PTR(ret);
|
||
|
|
|
||
|
|
switch (type) {
|
||
|
|
case G200_SE_A:
|
||
|
|
if (g200se->unique_rev_id >= 0x03)
|
||
|
|
info = &mgag200_g200se_a_03_device_info;
|
||
|
|
else if (g200se->unique_rev_id >= 0x02)
|
||
|
|
info = &mgag200_g200se_a_02_device_info;
|
||
|
|
else
|
||
|
|
info = &mgag200_g200se_a_01_device_info;
|
||
|
|
break;
|
||
|
|
case G200_SE_B:
|
||
|
|
if (g200se->unique_rev_id >= 0x03)
|
||
|
|
info = &mgag200_g200se_b_03_device_info;
|
||
|
|
else if (g200se->unique_rev_id >= 0x02)
|
||
|
|
info = &mgag200_g200se_b_02_device_info;
|
||
|
|
else
|
||
|
|
info = &mgag200_g200se_b_01_device_info;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return ERR_PTR(-EINVAL);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (g200se->unique_rev_id >= 0x04)
|
||
|
|
funcs = &mgag200_g200se_04_device_funcs;
|
||
|
|
else
|
||
|
|
funcs = &mgag200_g200se_00_device_funcs;
|
||
|
|
|
||
|
|
ret = mgag200_device_init(mdev, info, funcs);
|
||
|
|
if (ret)
|
||
|
|
return ERR_PTR(ret);
|
||
|
|
|
||
|
|
mgag200_g200se_init_registers(g200se);
|
||
|
|
|
||
|
|
vram_available = mgag200_device_probe_vram(mdev);
|
||
|
|
|
||
|
|
ret = mgag200_mode_config_init(mdev, vram_available);
|
||
|
|
if (ret)
|
||
|
|
return ERR_PTR(ret);
|
||
|
|
|
||
|
|
ret = mgag200_g200se_pipeline_init(mdev);
|
||
|
|
if (ret)
|
||
|
|
return ERR_PTR(ret);
|
||
|
|
|
||
|
|
drm_mode_config_reset(dev);
|
||
|
|
|
||
|
|
return mdev;
|
||
|
|
}
|