371 lines
11 KiB
C
371 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#include <drm/drm_crtc.h>
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#include <drm/drm_probe_helper.h>
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#include "mdp5_kms.h"
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static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
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{
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struct msm_drm_private *priv = encoder->dev->dev_private;
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return to_mdp5_kms(to_mdp_kms(priv->kms));
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}
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static void mdp5_encoder_destroy(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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drm_encoder_cleanup(encoder);
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kfree(mdp5_encoder);
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}
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static const struct drm_encoder_funcs mdp5_encoder_funcs = {
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.destroy = mdp5_encoder_destroy,
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};
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static void mdp5_vid_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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struct drm_device *dev = encoder->dev;
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struct drm_connector *connector;
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int intf = mdp5_encoder->intf->num;
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uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
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uint32_t display_v_start, display_v_end;
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uint32_t hsync_start_x, hsync_end_x;
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uint32_t format = 0x2100;
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unsigned long flags;
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mode = adjusted_mode;
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DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode));
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ctrl_pol = 0;
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/* DSI controller cannot handle active-low sync signals. */
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if (mdp5_encoder->intf->type != INTF_DSI) {
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
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}
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/* probably need to get DATA_EN polarity from panel.. */
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dtv_hsync_skew = 0; /* get this from panel? */
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/* Get color format from panel, default is 8bpc */
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder) {
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switch (connector->display_info.bpc) {
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case 4:
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format |= 0;
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break;
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case 5:
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format |= 0x15;
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break;
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case 6:
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format |= 0x2A;
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break;
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case 8:
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default:
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format |= 0x3F;
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break;
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}
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break;
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}
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}
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hsync_start_x = (mode->htotal - mode->hsync_start);
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hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
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vsync_period = mode->vtotal * mode->htotal;
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vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
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display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
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display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
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/*
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* For edp only:
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* DISPLAY_V_START = (VBP * HCYCLE) + HBP
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* DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
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*/
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if (mdp5_encoder->intf->type == INTF_eDP) {
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display_v_start += mode->htotal - mode->hsync_start;
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display_v_end -= mode->hsync_start - mode->hdisplay;
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}
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spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf),
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MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) |
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MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal));
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mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf),
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MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) |
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MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x));
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mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf),
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MDP5_INTF_ACTIVE_HCTL_START(0) |
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MDP5_INTF_ACTIVE_HCTL_END(0));
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mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3); /* frame+line? */
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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mdp5_crtc_set_pipeline(encoder->crtc);
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}
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static void mdp5_vid_encoder_disable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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struct mdp5_ctl *ctl = mdp5_encoder->ctl;
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struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
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struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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int intfn = mdp5_encoder->intf->num;
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unsigned long flags;
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if (WARN_ON(!mdp5_encoder->enabled))
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return;
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mdp5_ctl_set_encoder_state(ctl, pipeline, false);
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spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0);
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
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/*
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* Wait for a vsync so we know the ENABLE=0 latched before
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* the (connector) source of the vsync's gets disabled,
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* otherwise we end up in a funny state if we re-enable
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* before the disable latches, which results that some of
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* the settings changes for the new modeset (like new
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* scanout buffer) don't latch properly..
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*/
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mdp_irq_wait(&mdp5_kms->base, intf2vblank(mixer, intf));
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mdp5_encoder->enabled = false;
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}
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static void mdp5_vid_encoder_enable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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struct mdp5_ctl *ctl = mdp5_encoder->ctl;
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struct mdp5_interface *intf = mdp5_encoder->intf;
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struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
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int intfn = intf->num;
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unsigned long flags;
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if (WARN_ON(mdp5_encoder->enabled))
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return;
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spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1);
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
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mdp5_ctl_set_encoder_state(ctl, pipeline, true);
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mdp5_encoder->enabled = true;
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}
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static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
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mdp5_cmd_encoder_mode_set(encoder, mode, adjusted_mode);
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else
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mdp5_vid_encoder_mode_set(encoder, mode, adjusted_mode);
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}
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static void mdp5_encoder_disable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
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mdp5_cmd_encoder_disable(encoder);
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else
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mdp5_vid_encoder_disable(encoder);
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}
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static void mdp5_encoder_enable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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/* this isn't right I think */
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struct drm_crtc_state *cstate = encoder->crtc->state;
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mdp5_encoder_mode_set(encoder, &cstate->mode, &cstate->adjusted_mode);
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if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
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mdp5_cmd_encoder_enable(encoder);
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else
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mdp5_vid_encoder_enable(encoder);
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}
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static int mdp5_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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struct mdp5_ctl *ctl = mdp5_encoder->ctl;
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mdp5_cstate->ctl = ctl;
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mdp5_cstate->pipeline.intf = intf;
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/*
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* This is a bit awkward, but we want to flush the CTL and hit the
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* START bit at most once for an atomic update. In the non-full-
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* modeset case, this is done from crtc->atomic_flush(), but that
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* is too early in the case of full modeset, in which case we
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* defer to encoder->enable(). But we need to *know* whether
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* encoder->enable() will be called to do this:
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*/
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if (drm_atomic_crtc_needs_modeset(crtc_state))
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mdp5_cstate->defer_start = true;
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return 0;
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}
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static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
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.disable = mdp5_encoder_disable,
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.enable = mdp5_encoder_enable,
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.atomic_check = mdp5_encoder_atomic_check,
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};
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int mdp5_encoder_get_linecount(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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int intf = mdp5_encoder->intf->num;
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return mdp5_read(mdp5_kms, REG_MDP5_INTF_LINE_COUNT(intf));
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}
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u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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int intf = mdp5_encoder->intf->num;
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return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf));
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}
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int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
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struct drm_encoder *slave_encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder);
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struct mdp5_kms *mdp5_kms;
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struct device *dev;
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int intf_num;
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u32 data = 0;
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if (!encoder || !slave_encoder)
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return -EINVAL;
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mdp5_kms = get_kms(encoder);
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intf_num = mdp5_encoder->intf->num;
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/* Switch slave encoder's TimingGen Sync mode,
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* to use the master's enable signal for the slave encoder.
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*/
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if (intf_num == 1)
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data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
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else if (intf_num == 2)
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data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
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else
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return -EINVAL;
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dev = &mdp5_kms->pdev->dev;
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/* Make sure clocks are on when connectors calling this function. */
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pm_runtime_get_sync(dev);
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/* Dumb Panel, Sync mode */
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mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0);
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mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data);
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mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
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mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
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pm_runtime_put_sync(dev);
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return 0;
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}
|
||
|
|
|
||
|
|
void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode)
|
||
|
|
{
|
||
|
|
struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
|
||
|
|
struct mdp5_interface *intf = mdp5_encoder->intf;
|
||
|
|
|
||
|
|
/* TODO: Expand this to set writeback modes too */
|
||
|
|
if (cmd_mode) {
|
||
|
|
WARN_ON(intf->type != INTF_DSI);
|
||
|
|
intf->mode = MDP5_INTF_DSI_MODE_COMMAND;
|
||
|
|
} else {
|
||
|
|
if (intf->type == INTF_DSI)
|
||
|
|
intf->mode = MDP5_INTF_DSI_MODE_VIDEO;
|
||
|
|
else
|
||
|
|
intf->mode = MDP5_INTF_MODE_NONE;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* initialize encoder */
|
||
|
|
struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
|
||
|
|
struct mdp5_interface *intf,
|
||
|
|
struct mdp5_ctl *ctl)
|
||
|
|
{
|
||
|
|
struct drm_encoder *encoder = NULL;
|
||
|
|
struct mdp5_encoder *mdp5_encoder;
|
||
|
|
int enc_type = (intf->type == INTF_DSI) ?
|
||
|
|
DRM_MODE_ENCODER_DSI : DRM_MODE_ENCODER_TMDS;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL);
|
||
|
|
if (!mdp5_encoder) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
encoder = &mdp5_encoder->base;
|
||
|
|
mdp5_encoder->ctl = ctl;
|
||
|
|
mdp5_encoder->intf = intf;
|
||
|
|
|
||
|
|
spin_lock_init(&mdp5_encoder->intf_lock);
|
||
|
|
|
||
|
|
drm_encoder_init(dev, encoder, &mdp5_encoder_funcs, enc_type, NULL);
|
||
|
|
|
||
|
|
drm_encoder_helper_add(encoder, &mdp5_encoder_helper_funcs);
|
||
|
|
|
||
|
|
return encoder;
|
||
|
|
|
||
|
|
fail:
|
||
|
|
if (encoder)
|
||
|
|
mdp5_encoder_destroy(encoder);
|
||
|
|
|
||
|
|
return ERR_PTR(ret);
|
||
|
|
}
|