163 lines
13 KiB
C
163 lines
13 KiB
C
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/*******************************************************************************
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Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#ifndef _cla0b5_h_
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#define _cla0b5_h_
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#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260)
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#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0
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#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
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#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
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#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
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#define NVA0B5_SET_DST_PHYS_MODE (0x00000264)
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#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0
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#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
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#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
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#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
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#define NVA0B5_LAUNCH_DMA (0x00000300)
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#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
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#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000)
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#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001)
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#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002)
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#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2
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#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000)
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#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002)
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#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5
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#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000)
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#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001)
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#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002)
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#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7
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#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
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#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001)
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#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8
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#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
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#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001)
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#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9
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#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000)
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#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001)
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#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10
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#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000)
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#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001)
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#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11
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#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000)
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#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001)
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#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12
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#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000)
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#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
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#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13
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#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000)
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#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000)
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#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001)
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#define NVA0B5_OFFSET_IN_UPPER (0x00000400)
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#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0
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#define NVA0B5_OFFSET_IN_LOWER (0x00000404)
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#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0
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#define NVA0B5_OFFSET_OUT_UPPER (0x00000408)
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#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0
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#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C)
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#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0
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#define NVA0B5_PITCH_IN (0x00000410)
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#define NVA0B5_PITCH_IN_VALUE 31:0
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#define NVA0B5_PITCH_OUT (0x00000414)
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#define NVA0B5_PITCH_OUT_VALUE 31:0
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#define NVA0B5_LINE_LENGTH_IN (0x00000418)
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#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0
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#define NVA0B5_LINE_COUNT (0x0000041C)
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#define NVA0B5_LINE_COUNT_VALUE 31:0
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#define NVA0B5_SET_REMAP_CONST_A (0x00000700)
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#define NVA0B5_SET_REMAP_CONST_A_V 31:0
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#define NVA0B5_SET_REMAP_CONST_B (0x00000704)
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#define NVA0B5_SET_REMAP_CONST_B_V 31:0
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#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005)
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#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006)
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#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16
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#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000)
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#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001)
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#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002)
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#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003)
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000)
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001)
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002)
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003)
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000)
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001)
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002)
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#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003)
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#endif // _cla0b5_h
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