551 lines
15 KiB
C
551 lines
15 KiB
C
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/*
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* Copyright 2021 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include "cgrp.h"
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#include "chan.h"
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#include "chid.h"
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#include "runl.h"
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#include "runq.h"
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#include <core/gpuobj.h>
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#include <subdev/top.h>
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#include <subdev/vfn.h>
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#include <nvif/class.h>
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/*TODO: allocate? */
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#define GA100_FIFO_NONSTALL_VECTOR 0
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static u32
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ga100_chan_doorbell_handle(struct nvkm_chan *chan)
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{
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return (chan->cgrp->runl->doorbell << 16) | chan->id;
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}
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static void
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ga100_chan_stop(struct nvkm_chan *chan)
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{
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struct nvkm_runl *runl = chan->cgrp->runl;
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nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0x00000003);
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}
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static void
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ga100_chan_start(struct nvkm_chan *chan)
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{
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struct nvkm_runl *runl = chan->cgrp->runl;
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struct nvkm_device *device = runl->fifo->engine.subdev.device;
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const int gfid = 0;
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nvkm_wr32(device, runl->chan + (chan->id * 4), 0x00000002);
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nvkm_wr32(device, runl->addr + 0x0090, (gfid << 16) | chan->id); /* INTERNAL_DOORBELL. */
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}
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static void
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ga100_chan_unbind(struct nvkm_chan *chan)
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{
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struct nvkm_runl *runl = chan->cgrp->runl;
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nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0xffffffff);
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}
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static int
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ga100_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
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{
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const u32 limit2 = ilog2(length / 8);
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nvkm_kmap(chan->inst);
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nvkm_wo32(chan->inst, 0x010, 0x0000face);
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nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
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nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset));
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nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16));
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nvkm_wo32(chan->inst, 0x084, 0x20400000);
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nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm);
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nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
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nvkm_wo32(chan->inst, 0x0e8, chan->id);
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nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000));
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nvkm_wo32(chan->inst, 0x0f8, 0x80000000 | GA100_FIFO_NONSTALL_VECTOR);
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nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);
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nvkm_done(chan->inst);
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return 0;
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}
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static const struct nvkm_chan_func_ramfc
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ga100_chan_ramfc = {
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.write = ga100_chan_ramfc_write,
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.devm = 0xfff,
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.priv = true,
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};
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const struct nvkm_chan_func
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ga100_chan = {
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.inst = &gf100_chan_inst,
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.userd = &gv100_chan_userd,
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.ramfc = &ga100_chan_ramfc,
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.unbind = ga100_chan_unbind,
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.start = ga100_chan_start,
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.stop = ga100_chan_stop,
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.preempt = gk110_chan_preempt,
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.doorbell_handle = ga100_chan_doorbell_handle,
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};
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static void
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ga100_cgrp_preempt(struct nvkm_cgrp *cgrp)
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{
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struct nvkm_runl *runl = cgrp->runl;
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nvkm_wr32(runl->fifo->engine.subdev.device, runl->addr + 0x098, 0x01000000 | cgrp->id);
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}
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const struct nvkm_cgrp_func
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ga100_cgrp = {
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.preempt = ga100_cgrp_preempt,
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};
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static int
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ga100_engn_cxid(struct nvkm_engn *engn, bool *cgid)
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{
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struct nvkm_runl *runl = engn->runl;
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struct nvkm_device *device = runl->fifo->engine.subdev.device;
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u32 stat = nvkm_rd32(device, runl->addr + 0x200 + engn->id * 0x40);
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ENGN_DEBUG(engn, "status %08x", stat);
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*cgid = true;
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switch ((stat & 0x0000e000) >> 13) {
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case 0 /* INVALID */: return -ENODEV;
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case 1 /* VALID */:
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case 5 /* SAVE */: return (stat & 0x00000fff);
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case 6 /* LOAD */: return (stat & 0x0fff0000) >> 16;
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case 7 /* SWITCH */:
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if (nvkm_engine_chsw_load(engn->engine))
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return (stat & 0x0fff0000) >> 16;
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return (stat & 0x00000fff);
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default:
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WARN_ON(1);
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break;
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}
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return -ENODEV;
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}
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const struct nvkm_engn_func
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ga100_engn = {
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.cxid = ga100_engn_cxid,
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.ctor = gk104_ectx_ctor,
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.bind = gv100_ectx_bind,
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};
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const struct nvkm_engn_func
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ga100_engn_ce = {
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.cxid = ga100_engn_cxid,
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.ctor = gv100_ectx_ce_ctor,
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.bind = gv100_ectx_ce_bind,
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};
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static bool
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ga100_runq_idle(struct nvkm_runq *runq)
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{
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struct nvkm_device *device = runq->fifo->engine.subdev.device;
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return !(nvkm_rd32(device, 0x04015c + (runq->id * 0x800)) & 0x0000e000);
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}
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static bool
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ga100_runq_intr_1(struct nvkm_runq *runq, struct nvkm_runl *runl)
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{
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struct nvkm_device *device = runq->fifo->engine.subdev.device;
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u32 inte = nvkm_rd32(device, 0x040180 + (runq->id * 0x800));
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u32 intr = nvkm_rd32(device, 0x040148 + (runq->id * 0x800));
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u32 stat = intr & inte;
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if (!stat) {
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RUNQ_DEBUG(runq, "inte1 %08x %08x", intr, inte);
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return false;
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}
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if (stat & 0x80000000) {
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u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask;
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struct nvkm_chan *chan;
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unsigned long flags;
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RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid);
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chan = nvkm_runl_chan_get_chid(runl, chid, &flags);
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if (chan) {
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nvkm_chan_error(chan, true);
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nvkm_chan_put(&chan, flags);
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}
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nvkm_mask(device, 0x0400ac + (runq->id * 0x800), 0x00030000, 0x00030000);
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stat &= ~0x80000000;
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}
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if (stat) {
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RUNQ_ERROR(runq, "intr1 %08x", stat);
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nvkm_wr32(device, 0x0401a0 + (runq->id * 0x800), stat);
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}
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nvkm_wr32(device, 0x040148 + (runq->id * 0x800), intr);
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return true;
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}
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static bool
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ga100_runq_intr_0(struct nvkm_runq *runq, struct nvkm_runl *runl)
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{
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struct nvkm_device *device = runq->fifo->engine.subdev.device;
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u32 inte = nvkm_rd32(device, 0x040170 + (runq->id * 0x800));
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u32 intr = nvkm_rd32(device, 0x040108 + (runq->id * 0x800));
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u32 stat = intr & inte;
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if (!stat) {
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RUNQ_DEBUG(runq, "inte0 %08x %08x", intr, inte);
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return false;
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}
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/*TODO: expand on this when fixing up gf100's version. */
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if (stat & 0xc6afe000) {
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u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask;
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struct nvkm_chan *chan;
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unsigned long flags;
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RUNQ_ERROR(runq, "intr0 %08x", stat);
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chan = nvkm_runl_chan_get_chid(runl, chid, &flags);
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if (chan) {
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nvkm_chan_error(chan, true);
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nvkm_chan_put(&chan, flags);
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}
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stat &= ~0xc6afe000;
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}
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if (stat) {
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RUNQ_ERROR(runq, "intr0 %08x", stat);
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nvkm_wr32(device, 0x040190 + (runq->id * 0x800), stat);
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}
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nvkm_wr32(device, 0x040108 + (runq->id * 0x800), intr);
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return true;
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}
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static bool
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ga100_runq_intr(struct nvkm_runq *runq, struct nvkm_runl *runl)
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{
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bool intr0 = ga100_runq_intr_0(runq, runl);
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bool intr1 = ga100_runq_intr_1(runq, runl);
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return intr0 || intr1;
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}
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static void
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ga100_runq_init(struct nvkm_runq *runq)
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{
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struct nvkm_device *device = runq->fifo->engine.subdev.device;
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nvkm_wr32(device, 0x040108 + (runq->id * 0x800), 0xffffffff); /* INTR_0 */
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nvkm_wr32(device, 0x040148 + (runq->id * 0x800), 0xffffffff); /* INTR_1 */
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nvkm_wr32(device, 0x040170 + (runq->id * 0x800), 0xffffffff); /* INTR_0_EN_SET_TREE */
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nvkm_wr32(device, 0x040180 + (runq->id * 0x800), 0xffffffff); /* INTR_1_EN_SET_TREE */
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}
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const struct nvkm_runq_func
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ga100_runq = {
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.init = ga100_runq_init,
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.intr = ga100_runq_intr,
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.idle = ga100_runq_idle,
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};
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static bool
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ga100_runl_preempt_pending(struct nvkm_runl *runl)
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{
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return nvkm_rd32(runl->fifo->engine.subdev.device, runl->addr + 0x098) & 0x00100000;
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}
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static void
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ga100_runl_preempt(struct nvkm_runl *runl)
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{
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nvkm_wr32(runl->fifo->engine.subdev.device, runl->addr + 0x098, 0x00000000);
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}
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static void
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ga100_runl_allow(struct nvkm_runl *runl, u32 engm)
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{
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nvkm_mask(runl->fifo->engine.subdev.device, runl->addr + 0x094, 0x00000001, 0x00000000);
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}
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static void
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ga100_runl_block(struct nvkm_runl *runl, u32 engm)
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{
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nvkm_mask(runl->fifo->engine.subdev.device, runl->addr + 0x094, 0x00000001, 0x00000001);
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}
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static bool
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ga100_runl_pending(struct nvkm_runl *runl)
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{
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struct nvkm_device *device = runl->fifo->engine.subdev.device;
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return nvkm_rd32(device, runl->addr + 0x08c) & 0x00008000;
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}
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static void
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ga100_runl_commit(struct nvkm_runl *runl, struct nvkm_memory *memory, u32 start, int count)
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{
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struct nvkm_device *device = runl->fifo->engine.subdev.device;
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u64 addr = nvkm_memory_addr(memory) + start;
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nvkm_wr32(device, runl->addr + 0x080, lower_32_bits(addr));
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nvkm_wr32(device, runl->addr + 0x084, upper_32_bits(addr));
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nvkm_wr32(device, runl->addr + 0x088, count);
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}
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static irqreturn_t
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ga100_runl_intr(struct nvkm_inth *inth)
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{
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struct nvkm_runl *runl = container_of(inth, typeof(*runl), inth);
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struct nvkm_engn *engn;
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struct nvkm_device *device = runl->fifo->engine.subdev.device;
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u32 inte = nvkm_rd32(device, runl->addr + 0x120);
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u32 intr = nvkm_rd32(device, runl->addr + 0x100);
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u32 stat = intr & inte;
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u32 info;
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if (!stat) {
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RUNL_DEBUG(runl, "inte %08x %08x", intr, inte);
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return IRQ_NONE;
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}
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if (stat & 0x00000007) {
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nvkm_runl_foreach_engn_cond(engn, runl, stat & BIT(engn->id)) {
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info = nvkm_rd32(device, runl->addr + 0x224 + (engn->id * 0x40));
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tu102_fifo_intr_ctxsw_timeout_info(engn, info);
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||
|
|
|
||
|
|
nvkm_wr32(device, runl->addr + 0x100, BIT(engn->id));
|
||
|
|
stat &= ~BIT(engn->id);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (stat & 0x00000300) {
|
||
|
|
nvkm_wr32(device, runl->addr + 0x100, stat & 0x00000300);
|
||
|
|
stat &= ~0x00000300;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (stat & 0x00010000) {
|
||
|
|
if (runl->runq[0]) {
|
||
|
|
if (runl->runq[0]->func->intr(runl->runq[0], runl))
|
||
|
|
stat &= ~0x00010000;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (stat & 0x00020000) {
|
||
|
|
if (runl->runq[1]) {
|
||
|
|
if (runl->runq[1]->func->intr(runl->runq[1], runl))
|
||
|
|
stat &= ~0x00020000;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (stat) {
|
||
|
|
RUNL_ERROR(runl, "intr %08x", stat);
|
||
|
|
nvkm_wr32(device, runl->addr + 0x140, stat);
|
||
|
|
}
|
||
|
|
|
||
|
|
nvkm_wr32(device, runl->addr + 0x180, 0x00000001);
|
||
|
|
return IRQ_HANDLED;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
ga100_runl_fini(struct nvkm_runl *runl)
|
||
|
|
{
|
||
|
|
nvkm_mask(runl->fifo->engine.subdev.device, runl->addr + 0x300, 0x80000000, 0x00000000);
|
||
|
|
nvkm_inth_block(&runl->inth);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
ga100_runl_init(struct nvkm_runl *runl)
|
||
|
|
{
|
||
|
|
struct nvkm_fifo *fifo = runl->fifo;
|
||
|
|
struct nvkm_runq *runq;
|
||
|
|
struct nvkm_device *device = fifo->engine.subdev.device;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
/* Submit NULL runlist and preempt. */
|
||
|
|
nvkm_wr32(device, runl->addr + 0x088, 0x00000000);
|
||
|
|
runl->func->preempt(runl);
|
||
|
|
|
||
|
|
/* Enable doorbell. */
|
||
|
|
nvkm_mask(device, runl->addr + 0x300, 0x80000000, 0x80000000);
|
||
|
|
|
||
|
|
nvkm_wr32(device, runl->addr + 0x100, 0xffffffff); /* INTR_0 */
|
||
|
|
nvkm_wr32(device, runl->addr + 0x140, 0xffffffff); /* INTR_0_EN_CLEAR_TREE(0) */
|
||
|
|
nvkm_wr32(device, runl->addr + 0x120, 0x000f1307); /* INTR_0_EN_SET_TREE(0) */
|
||
|
|
nvkm_wr32(device, runl->addr + 0x148, 0xffffffff); /* INTR_0_EN_CLEAR_TREE(1) */
|
||
|
|
nvkm_wr32(device, runl->addr + 0x128, 0x00000000); /* INTR_0_EN_SET_TREE(1) */
|
||
|
|
|
||
|
|
/* Init PBDMA(s). */
|
||
|
|
for (i = 0; i < runl->runq_nr; i++) {
|
||
|
|
runq = runl->runq[i];
|
||
|
|
runq->func->init(runq);
|
||
|
|
}
|
||
|
|
|
||
|
|
nvkm_inth_allow(&runl->inth);
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct nvkm_runl_func
|
||
|
|
ga100_runl = {
|
||
|
|
.init = ga100_runl_init,
|
||
|
|
.fini = ga100_runl_fini,
|
||
|
|
.size = 16,
|
||
|
|
.update = nv50_runl_update,
|
||
|
|
.insert_cgrp = gv100_runl_insert_cgrp,
|
||
|
|
.insert_chan = gv100_runl_insert_chan,
|
||
|
|
.commit = ga100_runl_commit,
|
||
|
|
.wait = nv50_runl_wait,
|
||
|
|
.pending = ga100_runl_pending,
|
||
|
|
.block = ga100_runl_block,
|
||
|
|
.allow = ga100_runl_allow,
|
||
|
|
.preempt = ga100_runl_preempt,
|
||
|
|
.preempt_pending = ga100_runl_preempt_pending,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int
|
||
|
|
ga100_runl_new(struct nvkm_fifo *fifo, int id, u32 addr, struct nvkm_runl **prunl)
|
||
|
|
{
|
||
|
|
struct nvkm_device *device = fifo->engine.subdev.device;
|
||
|
|
struct nvkm_runl *runl;
|
||
|
|
u32 chcfg = nvkm_rd32(device, addr + 0x004);
|
||
|
|
u32 chnum = 1 << (chcfg & 0x0000000f);
|
||
|
|
u32 chaddr = (chcfg & 0xfffffff0);
|
||
|
|
u32 dbcfg = nvkm_rd32(device, addr + 0x008);
|
||
|
|
u32 vector = nvkm_rd32(device, addr + 0x160);
|
||
|
|
int i, ret;
|
||
|
|
|
||
|
|
runl = *prunl = nvkm_runl_new(fifo, id, addr, chnum);
|
||
|
|
if (IS_ERR(runl))
|
||
|
|
return PTR_ERR(runl);
|
||
|
|
|
||
|
|
for (i = 0; i < 2; i++) {
|
||
|
|
u32 pbcfg = nvkm_rd32(device, addr + 0x010 + (i * 0x04));
|
||
|
|
if (pbcfg & 0x80000000) {
|
||
|
|
runl->runq[runl->runq_nr] =
|
||
|
|
nvkm_runq_new(fifo, ((pbcfg & 0x03fffc00) - 0x040000) / 0x800);
|
||
|
|
if (!runl->runq[runl->runq_nr])
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
runl->runq_nr++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = nvkm_inth_add(&device->vfn->intr, vector & 0x00000fff, NVKM_INTR_PRIO_NORMAL,
|
||
|
|
&fifo->engine.subdev, ga100_runl_intr, &runl->inth);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
runl->chan = chaddr;
|
||
|
|
runl->doorbell = dbcfg >> 16;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static irqreturn_t
|
||
|
|
ga100_fifo_nonstall_intr(struct nvkm_inth *inth)
|
||
|
|
{
|
||
|
|
struct nvkm_fifo *fifo = container_of(inth, typeof(*fifo), nonstall.intr);
|
||
|
|
|
||
|
|
nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT);
|
||
|
|
return IRQ_HANDLED;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
ga100_fifo_nonstall_block(struct nvkm_event *event, int type, int index)
|
||
|
|
{
|
||
|
|
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
|
||
|
|
|
||
|
|
nvkm_inth_block(&fifo->nonstall.intr);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
ga100_fifo_nonstall_allow(struct nvkm_event *event, int type, int index)
|
||
|
|
{
|
||
|
|
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
|
||
|
|
|
||
|
|
nvkm_inth_allow(&fifo->nonstall.intr);
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct nvkm_event_func
|
||
|
|
ga100_fifo_nonstall = {
|
||
|
|
.init = ga100_fifo_nonstall_allow,
|
||
|
|
.fini = ga100_fifo_nonstall_block,
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)
|
||
|
|
{
|
||
|
|
return nvkm_inth_add(&fifo->engine.subdev.device->vfn->intr, GA100_FIFO_NONSTALL_VECTOR,
|
||
|
|
NVKM_INTR_PRIO_NORMAL, &fifo->engine.subdev, ga100_fifo_nonstall_intr,
|
||
|
|
&fifo->nonstall.intr);
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
ga100_fifo_runl_ctor(struct nvkm_fifo *fifo)
|
||
|
|
{
|
||
|
|
struct nvkm_device *device = fifo->engine.subdev.device;
|
||
|
|
struct nvkm_top_device *tdev;
|
||
|
|
struct nvkm_runl *runl;
|
||
|
|
int id = 0, ret;
|
||
|
|
|
||
|
|
nvkm_list_foreach(tdev, &device->top->device, head, tdev->runlist >= 0) {
|
||
|
|
runl = nvkm_runl_get(fifo, -1, tdev->runlist);
|
||
|
|
if (!runl) {
|
||
|
|
ret = ga100_runl_new(fifo, id++, tdev->runlist, &runl);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (tdev->engine < 0)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
nvkm_runl_add(runl, tdev->engine, (tdev->type == NVKM_ENGINE_CE) ?
|
||
|
|
fifo->func->engn_ce : fifo->func->engn, tdev->type, tdev->inst);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct nvkm_fifo_func
|
||
|
|
ga100_fifo = {
|
||
|
|
.runl_ctor = ga100_fifo_runl_ctor,
|
||
|
|
.mmu_fault = &tu102_fifo_mmu_fault,
|
||
|
|
.nonstall_ctor = ga100_fifo_nonstall_ctor,
|
||
|
|
.nonstall = &ga100_fifo_nonstall,
|
||
|
|
.runl = &ga100_runl,
|
||
|
|
.runq = &ga100_runq,
|
||
|
|
.engn = &ga100_engn,
|
||
|
|
.engn_ce = &ga100_engn_ce,
|
||
|
|
.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &ga100_cgrp, .force = true },
|
||
|
|
.chan = {{ 0, 0, AMPERE_CHANNEL_GPFIFO_A }, &ga100_chan },
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
ga100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
||
|
|
struct nvkm_fifo **pfifo)
|
||
|
|
{
|
||
|
|
return nvkm_fifo_new_(&ga100_fifo, device, type, inst, pfifo);
|
||
|
|
}
|