287 lines
7.7 KiB
C
287 lines
7.7 KiB
C
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/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include "cgrp.h"
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#include "chan.h"
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#include "runl.h"
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#include <core/memory.h>
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#include <subdev/mc.h>
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#include <subdev/vfn.h>
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#include <nvif/class.h>
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static u32
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tu102_chan_doorbell_handle(struct nvkm_chan *chan)
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{
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return (chan->cgrp->runl->id << 16) | chan->id;
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}
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static void
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tu102_chan_start(struct nvkm_chan *chan)
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{
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struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device;
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gk104_chan_start(chan);
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nvkm_wr32(device, device->vfn->addr.user + 0x0090, chan->func->doorbell_handle(chan));
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}
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static const struct nvkm_chan_func
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tu102_chan = {
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.inst = &gf100_chan_inst,
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.userd = &gv100_chan_userd,
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.ramfc = &gv100_chan_ramfc,
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.bind = gk104_chan_bind_inst,
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.unbind = gk104_chan_unbind,
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.start = tu102_chan_start,
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.stop = gk104_chan_stop,
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.preempt = gk110_chan_preempt,
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.doorbell_handle = tu102_chan_doorbell_handle,
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};
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static bool
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tu102_runl_pending(struct nvkm_runl *runl)
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{
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struct nvkm_device *device = runl->fifo->engine.subdev.device;
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return nvkm_rd32(device, 0x002b0c + (runl->id * 0x10)) & 0x00008000;
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}
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static void
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tu102_runl_commit(struct nvkm_runl *runl, struct nvkm_memory *memory, u32 start, int count)
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{
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struct nvkm_device *device = runl->fifo->engine.subdev.device;
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u64 addr = nvkm_memory_addr(memory) + start;
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/*XXX: target? */
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nvkm_wr32(device, 0x002b00 + (runl->id * 0x10), lower_32_bits(addr));
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nvkm_wr32(device, 0x002b04 + (runl->id * 0x10), upper_32_bits(addr));
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nvkm_wr32(device, 0x002b08 + (runl->id * 0x10), count);
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}
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static const struct nvkm_runl_func
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tu102_runl = {
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.runqs = 2,
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.size = 16,
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.update = nv50_runl_update,
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.insert_cgrp = gv100_runl_insert_cgrp,
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.insert_chan = gv100_runl_insert_chan,
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.commit = tu102_runl_commit,
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.wait = nv50_runl_wait,
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.pending = tu102_runl_pending,
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.block = gk104_runl_block,
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.allow = gk104_runl_allow,
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.preempt = gv100_runl_preempt,
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.preempt_pending = gf100_runl_preempt_pending,
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};
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static const struct nvkm_enum
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tu102_fifo_mmu_fault_engine[] = {
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{ 0x01, "DISPLAY" },
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{ 0x03, "PTP" },
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{ 0x06, "PWR_PMU" },
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{ 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
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{ 0x09, "PERF" },
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{ 0x1f, "PHYSICAL" },
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{ 0x20, "HOST0" },
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{ 0x21, "HOST1" },
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{ 0x22, "HOST2" },
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{ 0x23, "HOST3" },
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{ 0x24, "HOST4" },
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{ 0x25, "HOST5" },
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{ 0x26, "HOST6" },
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{ 0x27, "HOST7" },
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{ 0x28, "HOST8" },
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{ 0x29, "HOST9" },
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{ 0x2a, "HOST10" },
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{ 0x2b, "HOST11" },
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{ 0x2c, "HOST12" },
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{ 0x2d, "HOST13" },
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{ 0x2e, "HOST14" },
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{ 0x80, "BAR1", NULL, NVKM_SUBDEV_BAR },
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{ 0xc0, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
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{}
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};
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const struct nvkm_fifo_func_mmu_fault
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tu102_fifo_mmu_fault = {
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.recover = gf100_fifo_mmu_fault_recover,
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.access = gv100_fifo_mmu_fault_access,
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.engine = tu102_fifo_mmu_fault_engine,
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.reason = gv100_fifo_mmu_fault_reason,
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.hubclient = gv100_fifo_mmu_fault_hubclient,
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.gpcclient = gv100_fifo_mmu_fault_gpcclient,
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};
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void
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tu102_fifo_intr_ctxsw_timeout_info(struct nvkm_engn *engn, u32 info)
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{
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struct nvkm_runl *runl = engn->runl;
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struct nvkm_cgrp *cgrp;
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unsigned long flags;
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/* Check that engine hasn't become unstuck since timeout raised. */
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ENGN_DEBUG(engn, "CTXSW_TIMEOUT %08x", info);
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if (info & 0xc0000000)
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return;
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/* Determine channel group the engine is stuck on, and schedule recovery. */
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switch (info & 0x0000c000) {
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case 0x00004000: /* LOAD */
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cgrp = nvkm_runl_cgrp_get_cgid(runl, info & 0x3fff0000, &flags);
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break;
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case 0x00008000: /* SAVE */
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case 0x0000c000: /* SWITCH */
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cgrp = nvkm_runl_cgrp_get_cgid(runl, info & 0x00003fff, &flags);
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break;
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default:
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cgrp = NULL;
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break;
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}
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if (!WARN_ON(!cgrp)) {
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nvkm_runl_rc_cgrp(cgrp);
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nvkm_cgrp_put(&cgrp, flags);
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}
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}
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static void
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tu102_fifo_intr_ctxsw_timeout(struct nvkm_fifo *fifo)
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{
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struct nvkm_device *device = fifo->engine.subdev.device;
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struct nvkm_runl *runl;
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struct nvkm_engn *engn;
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u32 engm = nvkm_rd32(device, 0x002a30);
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u32 info;
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nvkm_runl_foreach(runl, fifo) {
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nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id)) {
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info = nvkm_rd32(device, 0x003200 + (engn->id * 4));
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tu102_fifo_intr_ctxsw_timeout_info(engn, info);
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}
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}
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nvkm_wr32(device, 0x002a30, engm);
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}
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static void
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tu102_fifo_intr_sched(struct nvkm_fifo *fifo)
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{
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struct nvkm_subdev *subdev = &fifo->engine.subdev;
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u32 intr = nvkm_rd32(subdev->device, 0x00254c);
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u32 code = intr & 0x000000ff;
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nvkm_error(subdev, "SCHED_ERROR %02x\n", code);
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}
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static irqreturn_t
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tu102_fifo_intr(struct nvkm_inth *inth)
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{
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struct nvkm_fifo *fifo = container_of(inth, typeof(*fifo), engine.subdev.inth);
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struct nvkm_subdev *subdev = &fifo->engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 mask = nvkm_rd32(device, 0x002140);
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u32 stat = nvkm_rd32(device, 0x002100) & mask;
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if (stat & 0x00000001) {
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gk104_fifo_intr_bind(fifo);
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nvkm_wr32(device, 0x002100, 0x00000001);
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stat &= ~0x00000001;
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}
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if (stat & 0x00000002) {
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tu102_fifo_intr_ctxsw_timeout(fifo);
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stat &= ~0x00000002;
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}
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if (stat & 0x00000100) {
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tu102_fifo_intr_sched(fifo);
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nvkm_wr32(device, 0x002100, 0x00000100);
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stat &= ~0x00000100;
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}
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if (stat & 0x00010000) {
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gk104_fifo_intr_chsw(fifo);
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nvkm_wr32(device, 0x002100, 0x00010000);
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stat &= ~0x00010000;
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}
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if (stat & 0x20000000) {
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if (gf100_fifo_intr_pbdma(fifo))
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stat &= ~0x20000000;
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}
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if (stat & 0x40000000) {
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gk104_fifo_intr_runlist(fifo);
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stat &= ~0x40000000;
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}
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if (stat & 0x80000000) {
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nvkm_wr32(device, 0x002100, 0x80000000);
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nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT);
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stat &= ~0x80000000;
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}
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if (stat) {
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nvkm_error(subdev, "INTR %08x\n", stat);
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spin_lock(&fifo->lock);
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nvkm_mask(device, 0x002140, stat, 0x00000000);
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spin_unlock(&fifo->lock);
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nvkm_wr32(device, 0x002100, stat);
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}
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return IRQ_HANDLED;
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}
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static void
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tu102_fifo_init_pbdmas(struct nvkm_fifo *fifo, u32 mask)
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{
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/* Not directly related to PBDMAs, but, enables doorbell to function. */
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nvkm_mask(fifo->engine.subdev.device, 0xb65000, 0x80000000, 0x80000000);
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}
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static const struct nvkm_fifo_func
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tu102_fifo = {
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.chid_nr = gm200_fifo_chid_nr,
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.chid_ctor = gk110_fifo_chid_ctor,
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.runq_nr = gm200_fifo_runq_nr,
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.runl_ctor = gk104_fifo_runl_ctor,
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.init = gk104_fifo_init,
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.init_pbdmas = tu102_fifo_init_pbdmas,
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.intr = tu102_fifo_intr,
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.mmu_fault = &tu102_fifo_mmu_fault,
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.nonstall = &gf100_fifo_nonstall,
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.runl = &tu102_runl,
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.runq = &gv100_runq,
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.engn = &gv100_engn,
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.engn_ce = &gv100_engn_ce,
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.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp, .force = true },
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.chan = {{ 0, 0, TURING_CHANNEL_GPFIFO_A }, &tu102_chan },
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};
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int
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tu102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_fifo **pfifo)
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{
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return nvkm_fifo_new_(&tu102_fifo, device, type, inst, pfifo);
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}
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