87 lines
3.1 KiB
C
87 lines
3.1 KiB
C
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/*
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* Copyright 2019 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <subdev/acr.h>
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#include <nvfw/sec2.h>
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static const struct nvkm_falcon_func
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tu102_sec2_flcn = {
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.disable = gm200_flcn_disable,
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.enable = gm200_flcn_enable,
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.reset_pmc = true,
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.reset_eng = gp102_flcn_reset_eng,
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.reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,
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.debug = 0x408,
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.bind_inst = gm200_flcn_bind_inst,
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.bind_stat = gm200_flcn_bind_stat,
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.bind_intr = true,
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.imem_pio = &gm200_flcn_imem_pio,
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.dmem_pio = &gm200_flcn_dmem_pio,
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.emem_addr = 0x01000000,
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.emem_pio = &gp102_flcn_emem_pio,
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.start = nvkm_falcon_v1_start,
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.cmdq = { 0xc00, 0xc04, 8 },
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.msgq = { 0xc80, 0xc84, 8 },
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};
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static const struct nvkm_sec2_func
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tu102_sec2 = {
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.flcn = &tu102_sec2_flcn,
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.unit_unload = NV_SEC2_UNIT_V2_UNLOAD,
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.unit_acr = NV_SEC2_UNIT_V2_ACR,
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.intr = gp102_sec2_intr,
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.initmsg = gp102_sec2_initmsg,
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};
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MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/tu104/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/tu104/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/tu104/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/tu106/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/tu106/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/tu106/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/tu116/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/tu116/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/tu116/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/tu117/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/tu117/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin");
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static const struct nvkm_sec2_fwif
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tu102_sec2_fwif[] = {
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{ 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 },
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{ -1, gp102_sec2_nofw, &tu102_sec2 }
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};
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int
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tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_sec2 **psec2)
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{
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/* TOP info wasn't updated on Turing to reflect the PRI
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* address change for some reason. We override it here.
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*/
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return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, 0x840000, psec2);
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}
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