246 lines
6.5 KiB
C
246 lines
6.5 KiB
C
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/*
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* Copyright 1993-2003 NVIDIA, Corporation
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* Copyright 2007-2009 Stuart Bennett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "pll.h"
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#include <subdev/bios.h>
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#include <subdev/bios/pll.h>
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static int
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getMNP_single(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk,
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int *pN, int *pM, int *pP)
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{
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/* Find M, N and P for a single stage PLL
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*
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* Note that some bioses (NV3x) have lookup tables of precomputed MNP
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* values, but we're too lazy to use those atm
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*
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* "clk" parameter in kHz
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* returns calculated clock
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*/
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struct nvkm_bios *bios = subdev->device->bios;
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int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq;
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int minM = info->vco1.min_m, maxM = info->vco1.max_m;
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int minN = info->vco1.min_n, maxN = info->vco1.max_n;
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int minU = info->vco1.min_inputfreq;
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int maxU = info->vco1.max_inputfreq;
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int minP = info->min_p;
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int maxP = info->max_p_usable;
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int crystal = info->refclk;
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int M, N, thisP, P;
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int clkP, calcclk;
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int delta, bestdelta = INT_MAX;
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int bestclk = 0;
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/* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
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/* possibly correlated with introduction of 27MHz crystal */
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if (bios->version.major < 0x60) {
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int cv = bios->version.chip;
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if (cv < 0x17 || cv == 0x1a || cv == 0x20) {
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if (clk > 250000)
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maxM = 6;
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if (clk > 340000)
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maxM = 2;
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} else if (cv < 0x40) {
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if (clk > 150000)
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maxM = 6;
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if (clk > 200000)
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maxM = 4;
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if (clk > 340000)
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maxM = 2;
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}
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}
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P = 1 << maxP;
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if ((clk * P) < minvco) {
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minvco = clk * maxP;
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maxvco = minvco * 2;
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}
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if (clk + clk/200 > maxvco) /* +0.5% */
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maxvco = clk + clk/200;
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/* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
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for (thisP = minP; thisP <= maxP; thisP++) {
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P = 1 << thisP;
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clkP = clk * P;
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if (clkP < minvco)
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continue;
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if (clkP > maxvco)
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return bestclk;
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for (M = minM; M <= maxM; M++) {
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if (crystal/M < minU)
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return bestclk;
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if (crystal/M > maxU)
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continue;
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/* add crystal/2 to round better */
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N = (clkP * M + crystal/2) / crystal;
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if (N < minN)
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continue;
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if (N > maxN)
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break;
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/* more rounding additions */
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calcclk = ((N * crystal + P/2) / P + M/2) / M;
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delta = abs(calcclk - clk);
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/* we do an exhaustive search rather than terminating
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* on an optimality condition...
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*/
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if (delta < bestdelta) {
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bestdelta = delta;
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bestclk = calcclk;
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*pN = N;
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*pM = M;
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*pP = thisP;
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if (delta == 0) /* except this one */
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return bestclk;
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}
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}
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}
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return bestclk;
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}
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static int
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getMNP_double(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk,
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int *pN1, int *pM1, int *pN2, int *pM2, int *pP)
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{
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/* Find M, N and P for a two stage PLL
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*
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* Note that some bioses (NV30+) have lookup tables of precomputed MNP
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* values, but we're too lazy to use those atm
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*
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* "clk" parameter in kHz
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* returns calculated clock
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*/
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int chip_version = subdev->device->bios->version.chip;
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int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq;
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int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq;
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int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq;
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int maxU1 = info->vco1.max_inputfreq, maxU2 = info->vco2.max_inputfreq;
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int minM1 = info->vco1.min_m, maxM1 = info->vco1.max_m;
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int minN1 = info->vco1.min_n, maxN1 = info->vco1.max_n;
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int minM2 = info->vco2.min_m, maxM2 = info->vco2.max_m;
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int minN2 = info->vco2.min_n, maxN2 = info->vco2.max_n;
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int maxlog2P = info->max_p_usable;
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int crystal = info->refclk;
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bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
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int M1, N1, M2, N2, log2P;
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int clkP, calcclk1, calcclk2, calcclkout;
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int delta, bestdelta = INT_MAX;
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int bestclk = 0;
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int vco2 = (maxvco2 - maxvco2/200) / 2;
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for (log2P = 0; clk && log2P < maxlog2P && clk <= (vco2 >> log2P); log2P++)
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;
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clkP = clk << log2P;
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if (maxvco2 < clk + clk/200) /* +0.5% */
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maxvco2 = clk + clk/200;
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for (M1 = minM1; M1 <= maxM1; M1++) {
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if (crystal/M1 < minU1)
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return bestclk;
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if (crystal/M1 > maxU1)
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continue;
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for (N1 = minN1; N1 <= maxN1; N1++) {
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calcclk1 = crystal * N1 / M1;
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if (calcclk1 < minvco1)
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continue;
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if (calcclk1 > maxvco1)
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break;
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for (M2 = minM2; M2 <= maxM2; M2++) {
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if (calcclk1/M2 < minU2)
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break;
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if (calcclk1/M2 > maxU2)
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continue;
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/* add calcclk1/2 to round better */
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N2 = (clkP * M2 + calcclk1/2) / calcclk1;
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if (N2 < minN2)
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continue;
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if (N2 > maxN2)
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break;
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if (!fixedgain2) {
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if (chip_version < 0x60)
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if (N2/M2 < 4 || N2/M2 > 10)
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continue;
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calcclk2 = calcclk1 * N2 / M2;
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if (calcclk2 < minvco2)
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break;
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if (calcclk2 > maxvco2)
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continue;
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} else
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calcclk2 = calcclk1;
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calcclkout = calcclk2 >> log2P;
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delta = abs(calcclkout - clk);
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/* we do an exhaustive search rather than terminating
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* on an optimality condition...
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*/
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if (delta < bestdelta) {
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bestdelta = delta;
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bestclk = calcclkout;
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*pN1 = N1;
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*pM1 = M1;
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*pN2 = N2;
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*pM2 = M2;
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*pP = log2P;
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if (delta == 0) /* except this one */
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return bestclk;
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}
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}
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}
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}
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return bestclk;
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}
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int
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nv04_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info, u32 freq,
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int *N1, int *M1, int *N2, int *M2, int *P)
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{
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int ret;
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if (!info->vco2.max_freq || !N2) {
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ret = getMNP_single(subdev, info, freq, N1, M1, P);
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if (N2) {
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*N2 = 1;
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*M2 = 1;
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}
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} else {
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ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
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}
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if (!ret)
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nvkm_error(subdev, "unable to compute acceptable pll values\n");
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return ret;
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}
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