194 lines
4.6 KiB
C
194 lines
4.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
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* Author: Rob Clark <rob@ti.com>
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* Andy Gross <andy.gross@ti.com>
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*/
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#ifndef OMAP_DMM_PRIV_H
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#define OMAP_DMM_PRIV_H
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#define DMM_REVISION 0x000
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#define DMM_HWINFO 0x004
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#define DMM_LISA_HWINFO 0x008
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#define DMM_DMM_SYSCONFIG 0x010
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#define DMM_LISA_LOCK 0x01C
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#define DMM_LISA_MAP__0 0x040
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#define DMM_LISA_MAP__1 0x044
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#define DMM_TILER_HWINFO 0x208
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#define DMM_TILER_OR__0 0x220
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#define DMM_TILER_OR__1 0x224
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#define DMM_PAT_HWINFO 0x408
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#define DMM_PAT_GEOMETRY 0x40C
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#define DMM_PAT_CONFIG 0x410
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#define DMM_PAT_VIEW__0 0x420
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#define DMM_PAT_VIEW__1 0x424
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#define DMM_PAT_VIEW_MAP__0 0x440
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#define DMM_PAT_VIEW_MAP_BASE 0x460
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#define DMM_PAT_IRQ_EOI 0x478
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#define DMM_PAT_IRQSTATUS_RAW 0x480
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#define DMM_PAT_IRQSTATUS 0x490
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#define DMM_PAT_IRQENABLE_SET 0x4A0
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#define DMM_PAT_IRQENABLE_CLR 0x4B0
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#define DMM_PAT_STATUS__0 0x4C0
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#define DMM_PAT_STATUS__1 0x4C4
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#define DMM_PAT_STATUS__2 0x4C8
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#define DMM_PAT_STATUS__3 0x4CC
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#define DMM_PAT_DESCR__0 0x500
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#define DMM_PAT_DESCR__1 0x510
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#define DMM_PAT_DESCR__2 0x520
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#define DMM_PAT_DESCR__3 0x530
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#define DMM_PEG_HWINFO 0x608
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#define DMM_PEG_PRIO 0x620
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#define DMM_PEG_PRIO_PAT 0x640
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#define DMM_IRQSTAT_DST (1<<0)
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#define DMM_IRQSTAT_LST (1<<1)
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#define DMM_IRQSTAT_ERR_INV_DSC (1<<2)
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#define DMM_IRQSTAT_ERR_INV_DATA (1<<3)
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#define DMM_IRQSTAT_ERR_UPD_AREA (1<<4)
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#define DMM_IRQSTAT_ERR_UPD_CTRL (1<<5)
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#define DMM_IRQSTAT_ERR_UPD_DATA (1<<6)
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#define DMM_IRQSTAT_ERR_LUT_MISS (1<<7)
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#define DMM_IRQSTAT_ERR_MASK (DMM_IRQSTAT_ERR_INV_DSC | \
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DMM_IRQSTAT_ERR_INV_DATA | \
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DMM_IRQSTAT_ERR_UPD_AREA | \
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DMM_IRQSTAT_ERR_UPD_CTRL | \
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DMM_IRQSTAT_ERR_UPD_DATA | \
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DMM_IRQSTAT_ERR_LUT_MISS)
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#define DMM_PATSTATUS_READY (1<<0)
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#define DMM_PATSTATUS_VALID (1<<1)
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#define DMM_PATSTATUS_RUN (1<<2)
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#define DMM_PATSTATUS_DONE (1<<3)
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#define DMM_PATSTATUS_LINKED (1<<4)
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#define DMM_PATSTATUS_BYPASSED (1<<7)
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#define DMM_PATSTATUS_ERR_INV_DESCR (1<<10)
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#define DMM_PATSTATUS_ERR_INV_DATA (1<<11)
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#define DMM_PATSTATUS_ERR_UPD_AREA (1<<12)
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#define DMM_PATSTATUS_ERR_UPD_CTRL (1<<13)
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#define DMM_PATSTATUS_ERR_UPD_DATA (1<<14)
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#define DMM_PATSTATUS_ERR_ACCESS (1<<15)
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/* note: don't treat DMM_PATSTATUS_ERR_ACCESS as an error */
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#define DMM_PATSTATUS_ERR (DMM_PATSTATUS_ERR_INV_DESCR | \
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DMM_PATSTATUS_ERR_INV_DATA | \
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DMM_PATSTATUS_ERR_UPD_AREA | \
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DMM_PATSTATUS_ERR_UPD_CTRL | \
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DMM_PATSTATUS_ERR_UPD_DATA)
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enum {
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PAT_STATUS,
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PAT_DESCR
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};
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struct pat_ctrl {
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u32 start:4;
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u32 dir:4;
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u32 lut_id:8;
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u32 sync:12;
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u32 ini:4;
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};
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struct pat {
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u32 next_pa;
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struct pat_area area;
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struct pat_ctrl ctrl;
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u32 data_pa;
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};
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#define DMM_FIXED_RETRY_COUNT 1000
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/* create refill buffer big enough to refill all slots, plus 3 descriptors..
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* 3 descriptors is probably the worst-case for # of 2d-slices in a 1d area,
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* but I guess you don't hit that worst case at the same time as full area
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* refill
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*/
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#define DESCR_SIZE 128
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#define REFILL_BUFFER_SIZE ((4 * 128 * 256) + (3 * DESCR_SIZE))
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/* For OMAP5, a fixed offset is added to all Y coordinates for 1D buffers.
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* This is used in programming to address the upper portion of the LUT
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*/
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#define OMAP5_LUT_OFFSET 128
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struct dmm;
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struct dmm_txn {
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void *engine_handle;
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struct tcm *tcm;
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u8 *current_va;
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dma_addr_t current_pa;
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struct pat *last_pat;
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};
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struct refill_engine {
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int id;
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struct dmm *dmm;
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struct tcm *tcm;
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u8 *refill_va;
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dma_addr_t refill_pa;
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/* only one trans per engine for now */
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struct dmm_txn txn;
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bool async;
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struct completion compl;
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struct list_head idle_node;
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};
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struct dmm_platform_data {
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u32 cpu_cache_flags;
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};
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struct dmm {
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struct device *dev;
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dma_addr_t phys_base;
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void __iomem *base;
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int irq;
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struct page *dummy_page;
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dma_addr_t dummy_pa;
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void *refill_va;
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dma_addr_t refill_pa;
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/* refill engines */
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wait_queue_head_t engine_queue;
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struct list_head idle_head;
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struct refill_engine *engines;
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int num_engines;
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atomic_t engine_counter;
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/* container information */
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int container_width;
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int container_height;
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int lut_width;
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int lut_height;
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int num_lut;
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/* array of LUT - TCM containers */
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struct tcm **tcm;
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/* allocation list and lock */
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struct list_head alloc_head;
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const struct dmm_platform_data *plat_data;
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bool dmm_workaround;
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spinlock_t wa_lock;
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u32 *wa_dma_data;
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dma_addr_t wa_dma_handle;
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struct dma_chan *wa_dma_chan;
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};
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#endif
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