306 lines
8.2 KiB
C
306 lines
8.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Unisoc Inc.
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*/
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#include <asm/div64.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/regmap.h>
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#include <linux/string.h>
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#include "sprd_dsi.h"
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#define L 0
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#define H 1
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#define CLK 0
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#define DATA 1
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#define INFINITY 0xffffffff
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#define MIN_OUTPUT_FREQ (100)
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#define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
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/* sharkle */
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#define VCO_BAND_LOW 750
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#define VCO_BAND_MID 1100
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#define VCO_BAND_HIGH 1500
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#define PHY_REF_CLK 26000
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static int dphy_calc_pll_param(struct dphy_pll *pll)
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{
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const u32 khz = 1000;
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const u32 mhz = 1000000;
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const unsigned long long factor = 100;
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unsigned long long tmp;
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int i;
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pll->potential_fvco = pll->freq / khz;
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pll->ref_clk = PHY_REF_CLK / khz;
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for (i = 0; i < 4; ++i) {
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if (pll->potential_fvco >= VCO_BAND_LOW &&
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pll->potential_fvco <= VCO_BAND_HIGH) {
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pll->fvco = pll->potential_fvco;
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pll->out_sel = BIT(i);
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break;
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}
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pll->potential_fvco <<= 1;
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}
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if (pll->fvco == 0)
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return -EINVAL;
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if (pll->fvco >= VCO_BAND_LOW && pll->fvco <= VCO_BAND_MID) {
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/* vco band control */
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pll->vco_band = 0x0;
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/* low pass filter control */
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pll->lpf_sel = 1;
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} else if (pll->fvco > VCO_BAND_MID && pll->fvco <= VCO_BAND_HIGH) {
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pll->vco_band = 0x1;
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pll->lpf_sel = 0;
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} else {
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return -EINVAL;
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}
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pll->nint = pll->fvco / pll->ref_clk;
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tmp = pll->fvco * factor * mhz;
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do_div(tmp, pll->ref_clk);
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tmp = tmp - pll->nint * factor * mhz;
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tmp *= BIT(20);
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do_div(tmp, 100000000);
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pll->kint = (u32)tmp;
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pll->refin = 3; /* pre-divider bypass */
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pll->sdm_en = true; /* use fraction N PLL */
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pll->fdk_s = 0x1; /* fraction */
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pll->cp_s = 0x0;
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pll->det_delay = 0x1;
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return 0;
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}
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static void dphy_set_pll_reg(struct dphy_pll *pll, struct regmap *regmap)
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{
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u8 reg_val[9] = {0};
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int i;
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u8 reg_addr[] = {
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0x03, 0x04, 0x06, 0x08, 0x09,
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0x0a, 0x0b, 0x0e, 0x0f
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};
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reg_val[0] = 1 | (1 << 1) | (pll->lpf_sel << 2);
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reg_val[1] = pll->div | (1 << 3) | (pll->cp_s << 5) | (pll->fdk_s << 7);
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reg_val[2] = pll->nint;
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reg_val[3] = pll->vco_band | (pll->sdm_en << 1) | (pll->refin << 2);
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reg_val[4] = pll->kint >> 12;
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reg_val[5] = pll->kint >> 4;
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reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf);
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reg_val[7] = 1 << 4;
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reg_val[8] = pll->det_delay;
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for (i = 0; i < sizeof(reg_addr); ++i) {
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regmap_write(regmap, reg_addr[i], reg_val[i]);
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DRM_DEBUG("%02x: %02x\n", reg_addr[i], reg_val[i]);
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}
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}
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int dphy_pll_config(struct dsi_context *ctx)
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{
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struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
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struct regmap *regmap = ctx->regmap;
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struct dphy_pll *pll = &ctx->pll;
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int ret;
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pll->freq = dsi->slave->hs_rate;
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/* FREQ = 26M * (NINT + KINT / 2^20) / out_sel */
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ret = dphy_calc_pll_param(pll);
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if (ret) {
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drm_err(dsi->drm, "failed to calculate dphy pll parameters\n");
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return ret;
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}
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dphy_set_pll_reg(pll, regmap);
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return 0;
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}
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static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[])
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{
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switch (type) {
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case REQUEST_TIME:
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regmap_write(regmap, 0x31, val[CLK]);
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regmap_write(regmap, 0x41, val[DATA]);
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regmap_write(regmap, 0x51, val[DATA]);
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regmap_write(regmap, 0x61, val[DATA]);
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regmap_write(regmap, 0x71, val[DATA]);
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regmap_write(regmap, 0x90, val[CLK]);
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regmap_write(regmap, 0xa0, val[DATA]);
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regmap_write(regmap, 0xb0, val[DATA]);
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regmap_write(regmap, 0xc0, val[DATA]);
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regmap_write(regmap, 0xd0, val[DATA]);
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break;
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case PREPARE_TIME:
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regmap_write(regmap, 0x32, val[CLK]);
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regmap_write(regmap, 0x42, val[DATA]);
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regmap_write(regmap, 0x52, val[DATA]);
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regmap_write(regmap, 0x62, val[DATA]);
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regmap_write(regmap, 0x72, val[DATA]);
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regmap_write(regmap, 0x91, val[CLK]);
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regmap_write(regmap, 0xa1, val[DATA]);
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regmap_write(regmap, 0xb1, val[DATA]);
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regmap_write(regmap, 0xc1, val[DATA]);
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regmap_write(regmap, 0xd1, val[DATA]);
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break;
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case ZERO_TIME:
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regmap_write(regmap, 0x33, val[CLK]);
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regmap_write(regmap, 0x43, val[DATA]);
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regmap_write(regmap, 0x53, val[DATA]);
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regmap_write(regmap, 0x63, val[DATA]);
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regmap_write(regmap, 0x73, val[DATA]);
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regmap_write(regmap, 0x92, val[CLK]);
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regmap_write(regmap, 0xa2, val[DATA]);
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regmap_write(regmap, 0xb2, val[DATA]);
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regmap_write(regmap, 0xc2, val[DATA]);
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regmap_write(regmap, 0xd2, val[DATA]);
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break;
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case TRAIL_TIME:
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regmap_write(regmap, 0x34, val[CLK]);
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regmap_write(regmap, 0x44, val[DATA]);
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regmap_write(regmap, 0x54, val[DATA]);
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regmap_write(regmap, 0x64, val[DATA]);
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regmap_write(regmap, 0x74, val[DATA]);
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regmap_write(regmap, 0x93, val[CLK]);
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regmap_write(regmap, 0xa3, val[DATA]);
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regmap_write(regmap, 0xb3, val[DATA]);
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regmap_write(regmap, 0xc3, val[DATA]);
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regmap_write(regmap, 0xd3, val[DATA]);
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break;
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case EXIT_TIME:
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regmap_write(regmap, 0x36, val[CLK]);
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regmap_write(regmap, 0x46, val[DATA]);
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regmap_write(regmap, 0x56, val[DATA]);
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regmap_write(regmap, 0x66, val[DATA]);
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regmap_write(regmap, 0x76, val[DATA]);
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regmap_write(regmap, 0x95, val[CLK]);
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regmap_write(regmap, 0xA5, val[DATA]);
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regmap_write(regmap, 0xB5, val[DATA]);
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regmap_write(regmap, 0xc5, val[DATA]);
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regmap_write(regmap, 0xd5, val[DATA]);
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break;
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case CLKPOST_TIME:
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regmap_write(regmap, 0x35, val[CLK]);
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regmap_write(regmap, 0x94, val[CLK]);
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break;
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/* the following just use default value */
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case SETTLE_TIME:
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fallthrough;
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case TA_GET:
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fallthrough;
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case TA_GO:
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fallthrough;
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case TA_SURE:
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fallthrough;
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default:
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break;
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}
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}
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void dphy_timing_config(struct dsi_context *ctx)
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{
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struct regmap *regmap = ctx->regmap;
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struct dphy_pll *pll = &ctx->pll;
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const u32 factor = 2;
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const u32 scale = 100;
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u32 t_ui, t_byteck, t_half_byteck;
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u32 range[2], constant;
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u8 val[2];
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u32 tmp = 0;
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/* t_ui: 1 ui, byteck: 8 ui, half byteck: 4 ui */
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t_ui = 1000 * scale / (pll->freq / 1000);
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t_byteck = t_ui << 3;
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t_half_byteck = t_ui << 2;
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constant = t_ui << 1;
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/* REQUEST_TIME: HS T-LPX: LP-01
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* For T-LPX, mipi spec defined min value is 50ns,
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* but maybe it shouldn't be too small, because BTA,
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* LP-10, LP-00, LP-01, all of this is related to T-LPX.
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*/
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range[L] = 50 * scale;
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range[H] = INFINITY;
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val[CLK] = DIV_ROUND_UP(range[L] * (factor << 1), t_byteck) - 2;
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val[DATA] = val[CLK];
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dphy_set_timing_reg(regmap, REQUEST_TIME, val);
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/* PREPARE_TIME: HS sequence: LP-00 */
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range[L] = 38 * scale;
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range[H] = 95 * scale;
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tmp = AVERAGE(range[L], range[H]);
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val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1;
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range[L] = 40 * scale + 4 * t_ui;
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range[H] = 85 * scale + 6 * t_ui;
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tmp |= AVERAGE(range[L], range[H]) << 16;
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val[DATA] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1;
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dphy_set_timing_reg(regmap, PREPARE_TIME, val);
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/* ZERO_TIME: HS-ZERO */
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range[L] = 300 * scale;
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range[H] = INFINITY;
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val[CLK] = DIV_ROUND_UP(range[L] * factor + (tmp & 0xffff)
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- 525 * t_byteck / 100, t_byteck) - 2;
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range[L] = 145 * scale + 10 * t_ui;
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val[DATA] = DIV_ROUND_UP(range[L] * factor
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+ ((tmp >> 16) & 0xffff) - 525 * t_byteck / 100,
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t_byteck) - 2;
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dphy_set_timing_reg(regmap, ZERO_TIME, val);
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/* TRAIL_TIME: HS-TRAIL */
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range[L] = 60 * scale;
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range[H] = INFINITY;
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val[CLK] = DIV_ROUND_UP(range[L] * factor - constant, t_half_byteck);
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range[L] = max(8 * t_ui, 60 * scale + 4 * t_ui);
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val[DATA] = DIV_ROUND_UP(range[L] * 3 / 2 - constant, t_half_byteck) - 2;
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dphy_set_timing_reg(regmap, TRAIL_TIME, val);
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/* EXIT_TIME: */
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range[L] = 100 * scale;
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range[H] = INFINITY;
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val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
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val[DATA] = val[CLK];
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dphy_set_timing_reg(regmap, EXIT_TIME, val);
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/* CLKPOST_TIME: */
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range[L] = 60 * scale + 52 * t_ui;
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range[H] = INFINITY;
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val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
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val[DATA] = val[CLK];
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dphy_set_timing_reg(regmap, CLKPOST_TIME, val);
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/* SETTLE_TIME:
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* This time is used for receiver. So for transmitter,
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* it can be ignored.
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*/
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/* TA_GO:
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* transmitter drives bridge state(LP-00) before releasing control,
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* reg 0x1f default value: 0x04, which is good.
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*/
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/* TA_SURE:
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* After LP-10 state and before bridge state(LP-00),
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* reg 0x20 default value: 0x01, which is good.
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*/
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/* TA_GET:
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* receiver drives Bridge state(LP-00) before releasing control
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* reg 0x21 default value: 0x03, which is good.
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*/
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}
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