69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef UDL_PROTO_H
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#define UDL_PROTO_H
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#include <linux/bits.h>
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#define UDL_MSG_BULK 0xaf
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/* Register access */
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#define UDL_CMD_WRITEREG 0x20 /* See register constants below */
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/* Framebuffer access */
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#define UDL_CMD_WRITERAW8 0x60 /* 8 bit raw write command. */
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#define UDL_CMD_WRITERL8 0x61 /* 8 bit run length command. */
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#define UDL_CMD_WRITECOPY8 0x62 /* 8 bit copy command. */
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#define UDL_CMD_WRITERLX8 0x63 /* 8 bit extended run length command. */
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#define UDL_CMD_WRITERAW16 0x68 /* 16 bit raw write command. */
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#define UDL_CMD_WRITERL16 0x69 /* 16 bit run length command. */
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#define UDL_CMD_WRITECOPY16 0x6a /* 16 bit copy command. */
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#define UDL_CMD_WRITERLX16 0x6b /* 16 bit extended run length command. */
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/* Color depth */
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#define UDL_REG_COLORDEPTH 0x00
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#define UDL_COLORDEPTH_16BPP 0
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#define UDL_COLORDEPTH_24BPP 1
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/* Display-mode settings */
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#define UDL_REG_XDISPLAYSTART 0x01
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#define UDL_REG_XDISPLAYEND 0x03
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#define UDL_REG_YDISPLAYSTART 0x05
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#define UDL_REG_YDISPLAYEND 0x07
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#define UDL_REG_XENDCOUNT 0x09
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#define UDL_REG_HSYNCSTART 0x0b
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#define UDL_REG_HSYNCEND 0x0d
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#define UDL_REG_HPIXELS 0x0f
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#define UDL_REG_YENDCOUNT 0x11
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#define UDL_REG_VSYNCSTART 0x13
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#define UDL_REG_VSYNCEND 0x15
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#define UDL_REG_VPIXELS 0x17
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#define UDL_REG_PIXELCLOCK5KHZ 0x1b
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/* On/Off for driving the DisplayLink framebuffer to the display */
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#define UDL_REG_BLANKMODE 0x1f
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#define UDL_BLANKMODE_ON 0x00 /* hsync and vsync on, visible */
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#define UDL_BLANKMODE_BLANKED 0x01 /* hsync and vsync on, blanked */
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#define UDL_BLANKMODE_VSYNC_OFF 0x03 /* vsync off, blanked */
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#define UDL_BLANKMODE_HSYNC_OFF 0x05 /* hsync off, blanked */
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#define UDL_BLANKMODE_POWERDOWN 0x07 /* powered off; requires modeset */
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/* Framebuffer address */
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#define UDL_REG_BASE16BPP_ADDR2 0x20
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#define UDL_REG_BASE16BPP_ADDR1 0x21
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#define UDL_REG_BASE16BPP_ADDR0 0x22
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#define UDL_REG_BASE8BPP_ADDR2 0x26
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#define UDL_REG_BASE8BPP_ADDR1 0x27
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#define UDL_REG_BASE8BPP_ADDR0 0x28
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#define UDL_BASE_ADDR0_MASK GENMASK(7, 0)
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#define UDL_BASE_ADDR1_MASK GENMASK(15, 8)
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#define UDL_BASE_ADDR2_MASK GENMASK(23, 16)
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/* Lock/unlock video registers */
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#define UDL_REG_VIDREG 0xff
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#define UDL_VIDREG_LOCK 0x00
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#define UDL_VIDREG_UNLOCK 0xff
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#endif
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