509 lines
14 KiB
C
509 lines
14 KiB
C
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#ifndef _VC4_HDMI_REGS_H_
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#define _VC4_HDMI_REGS_H_
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#include <linux/pm_runtime.h>
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#include "vc4_hdmi.h"
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#define VC4_HDMI_PACKET_STRIDE 0x24
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enum vc4_hdmi_regs {
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VC4_INVALID = 0,
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VC4_HDMI,
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VC4_HD,
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VC5_CEC,
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VC5_CSC,
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VC5_DVP,
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VC5_PHY,
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VC5_RAM,
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VC5_RM,
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};
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enum vc4_hdmi_field {
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HDMI_AUDIO_PACKET_CONFIG,
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HDMI_CEC_CNTRL_1,
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HDMI_CEC_CNTRL_2,
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HDMI_CEC_CNTRL_3,
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HDMI_CEC_CNTRL_4,
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HDMI_CEC_CNTRL_5,
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HDMI_CEC_CPU_CLEAR,
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HDMI_CEC_CPU_MASK_CLEAR,
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HDMI_CEC_CPU_MASK_SET,
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HDMI_CEC_CPU_MASK_STATUS,
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HDMI_CEC_CPU_STATUS,
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HDMI_CEC_CPU_SET,
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/*
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* Transmit data, first byte is low byte of the 32-bit reg.
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* MSB of each byte transmitted first.
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*/
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HDMI_CEC_RX_DATA_1,
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HDMI_CEC_RX_DATA_2,
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HDMI_CEC_RX_DATA_3,
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HDMI_CEC_RX_DATA_4,
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HDMI_CEC_TX_DATA_1,
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HDMI_CEC_TX_DATA_2,
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HDMI_CEC_TX_DATA_3,
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HDMI_CEC_TX_DATA_4,
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HDMI_CLOCK_STOP,
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HDMI_CORE_REV,
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HDMI_CRP_CFG,
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HDMI_CSC_12_11,
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HDMI_CSC_14_13,
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HDMI_CSC_22_21,
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HDMI_CSC_24_23,
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HDMI_CSC_32_31,
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HDMI_CSC_34_33,
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HDMI_CSC_CHANNEL_CTL,
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HDMI_CSC_CTL,
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/*
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* 20-bit fields containing CTS values to be transmitted if
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* !EXTERNAL_CTS_EN
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*/
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HDMI_CTS_0,
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HDMI_CTS_1,
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HDMI_DEEP_COLOR_CONFIG_1,
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HDMI_DVP_CTL,
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HDMI_FIFO_CTL,
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HDMI_FRAME_COUNT,
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HDMI_GCP_CONFIG,
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HDMI_GCP_WORD_1,
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HDMI_HORZA,
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HDMI_HORZB,
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HDMI_HOTPLUG,
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HDMI_HOTPLUG_INT,
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/*
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* 3 bits per field, where each field maps from that
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* corresponding MAI bus channel to the given HDMI channel.
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*/
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HDMI_MAI_CHANNEL_MAP,
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HDMI_MAI_CONFIG,
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HDMI_MAI_CTL,
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/*
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* Register for DMAing in audio data to be transported over
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* the MAI bus to the Falcon core.
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*/
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HDMI_MAI_DATA,
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/* Format header to be placed on the MAI data. Unused. */
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HDMI_MAI_FMT,
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/* Last received format word on the MAI bus. */
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HDMI_MAI_FORMAT,
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HDMI_MAI_SMP,
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HDMI_MAI_THR,
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HDMI_M_CTL,
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HDMI_RAM_PACKET_CONFIG,
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HDMI_RAM_PACKET_START,
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HDMI_RAM_PACKET_STATUS,
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HDMI_RM_CONTROL,
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HDMI_RM_FORMAT,
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HDMI_RM_OFFSET,
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HDMI_SCHEDULER_CONTROL,
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HDMI_SCRAMBLER_CTL,
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HDMI_SW_RESET_CONTROL,
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HDMI_TX_PHY_CHANNEL_SWAP,
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HDMI_TX_PHY_CLK_DIV,
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HDMI_TX_PHY_CTL_0,
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HDMI_TX_PHY_CTL_1,
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HDMI_TX_PHY_CTL_2,
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HDMI_TX_PHY_CTL_3,
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HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
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HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
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HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
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HDMI_TX_PHY_PLL_CFG,
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HDMI_TX_PHY_PLL_CTL_0,
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HDMI_TX_PHY_PLL_CTL_1,
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HDMI_TX_PHY_POWERDOWN_CTL,
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HDMI_TX_PHY_RESET_CTL,
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HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
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HDMI_VEC_INTERFACE_CFG,
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HDMI_VEC_INTERFACE_XBAR,
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HDMI_VERTA0,
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HDMI_VERTA1,
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HDMI_VERTB0,
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HDMI_VERTB1,
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HDMI_VID_CTL,
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HDMI_MISC_CONTROL,
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HDMI_FORMAT_DET_1,
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HDMI_FORMAT_DET_2,
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HDMI_FORMAT_DET_3,
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HDMI_FORMAT_DET_4,
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HDMI_FORMAT_DET_5,
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HDMI_FORMAT_DET_6,
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HDMI_FORMAT_DET_7,
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HDMI_FORMAT_DET_8,
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HDMI_FORMAT_DET_9,
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HDMI_FORMAT_DET_10,
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};
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struct vc4_hdmi_register {
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char *name;
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enum vc4_hdmi_regs reg;
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unsigned int offset;
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};
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#define _VC4_REG(_base, _reg, _offset) \
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[_reg] = { \
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.name = #_reg, \
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.reg = _base, \
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.offset = _offset, \
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}
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#define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset)
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#define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset)
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#define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset)
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#define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset)
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#define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset)
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#define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset)
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#define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset)
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#define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset)
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static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {
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VC4_HD_REG(HDMI_M_CTL, 0x000c),
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VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
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VC4_HD_REG(HDMI_MAI_THR, 0x0018),
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VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
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VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
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VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
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VC4_HD_REG(HDMI_VID_CTL, 0x0038),
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VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
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VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
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VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
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VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
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VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
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VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
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VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
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VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
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VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
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VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
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VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
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VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
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VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
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VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
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VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
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VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
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VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
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VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
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VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
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VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
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VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
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VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
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VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
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VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
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VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
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VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
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VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
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VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
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VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
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VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x00e4),
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VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
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VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
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VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
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VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
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VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
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VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
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VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
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VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
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VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
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VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
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VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
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VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
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VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
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VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
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VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
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VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
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VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
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VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
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VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
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VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
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VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
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VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
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};
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static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
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VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
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VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
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VC4_HD_REG(HDMI_MAI_THR, 0x0014),
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VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
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VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
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VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
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VC4_HD_REG(HDMI_VID_CTL, 0x0044),
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VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
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VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
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VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
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VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
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VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
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VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
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VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
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VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
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VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
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VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
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VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
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VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
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VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
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VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
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VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
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VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
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VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
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VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
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VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x134),
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VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x138),
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VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x13c),
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VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x140),
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VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x144),
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VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x148),
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VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x14c),
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VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x150),
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VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x154),
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VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x158),
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VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
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VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
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VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
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VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
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VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
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VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
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VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
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VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
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VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
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VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
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VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
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VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
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VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
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VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
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VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
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VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
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VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
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VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
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VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
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VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
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VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
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VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
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VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
|
||
|
|
|
||
|
|
VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
|
||
|
|
VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
|
||
|
|
VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
|
||
|
|
|
||
|
|
VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
|
||
|
|
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
|
||
|
|
|
||
|
|
VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
|
||
|
|
VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
|
||
|
|
VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
|
||
|
|
VC4_HD_REG(HDMI_MAI_THR, 0x0034),
|
||
|
|
VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
|
||
|
|
VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
|
||
|
|
VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
|
||
|
|
VC4_HD_REG(HDMI_VID_CTL, 0x0048),
|
||
|
|
VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
|
||
|
|
|
||
|
|
VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
|
||
|
|
VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
|
||
|
|
VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
|
||
|
|
VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
|
||
|
|
VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
|
||
|
|
VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
|
||
|
|
VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
|
||
|
|
VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
|
||
|
|
VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
|
||
|
|
VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
|
||
|
|
VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
|
||
|
|
VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
|
||
|
|
VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
|
||
|
|
VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
|
||
|
|
VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
|
||
|
|
VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
|
||
|
|
VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x134),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x138),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x13c),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x140),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x144),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x148),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x14c),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x150),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x154),
|
||
|
|
VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x158),
|
||
|
|
VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
|
||
|
|
VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
|
||
|
|
VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
|
||
|
|
VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
|
||
|
|
VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
|
||
|
|
|
||
|
|
VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
|
||
|
|
VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
|
||
|
|
VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
|
||
|
|
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
|
||
|
|
VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
|
||
|
|
|
||
|
|
VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
|
||
|
|
VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
|
||
|
|
VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
|
||
|
|
|
||
|
|
VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
|
||
|
|
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
|
||
|
|
VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
|
||
|
|
|
||
|
|
VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
|
||
|
|
VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
|
||
|
|
};
|
||
|
|
|
||
|
|
static inline
|
||
|
|
void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi,
|
||
|
|
enum vc4_hdmi_regs reg)
|
||
|
|
{
|
||
|
|
switch (reg) {
|
||
|
|
case VC4_HD:
|
||
|
|
return hdmi->hd_regs;
|
||
|
|
|
||
|
|
case VC4_HDMI:
|
||
|
|
return hdmi->hdmicore_regs;
|
||
|
|
|
||
|
|
case VC5_CSC:
|
||
|
|
return hdmi->csc_regs;
|
||
|
|
|
||
|
|
case VC5_CEC:
|
||
|
|
return hdmi->cec_regs;
|
||
|
|
|
||
|
|
case VC5_DVP:
|
||
|
|
return hdmi->dvp_regs;
|
||
|
|
|
||
|
|
case VC5_PHY:
|
||
|
|
return hdmi->phy_regs;
|
||
|
|
|
||
|
|
case VC5_RAM:
|
||
|
|
return hdmi->ram_regs;
|
||
|
|
|
||
|
|
case VC5_RM:
|
||
|
|
return hdmi->rm_regs;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi,
|
||
|
|
enum vc4_hdmi_field reg)
|
||
|
|
{
|
||
|
|
const struct vc4_hdmi_register *field;
|
||
|
|
const struct vc4_hdmi_variant *variant = hdmi->variant;
|
||
|
|
void __iomem *base;
|
||
|
|
|
||
|
|
WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
|
||
|
|
|
||
|
|
kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
|
||
|
|
|
||
|
|
if (reg >= variant->num_registers) {
|
||
|
|
dev_warn(&hdmi->pdev->dev,
|
||
|
|
"Invalid register ID %u\n", reg);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
field = &variant->registers[reg];
|
||
|
|
base = __vc4_hdmi_get_field_base(hdmi, field->reg);
|
||
|
|
if (!base) {
|
||
|
|
dev_warn(&hdmi->pdev->dev,
|
||
|
|
"Unknown register ID %u\n", reg);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
return readl(base + field->offset);
|
||
|
|
}
|
||
|
|
#define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg)
|
||
|
|
|
||
|
|
static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi,
|
||
|
|
enum vc4_hdmi_field reg,
|
||
|
|
u32 value)
|
||
|
|
{
|
||
|
|
const struct vc4_hdmi_register *field;
|
||
|
|
const struct vc4_hdmi_variant *variant = hdmi->variant;
|
||
|
|
void __iomem *base;
|
||
|
|
|
||
|
|
lockdep_assert_held(&hdmi->hw_lock);
|
||
|
|
|
||
|
|
WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
|
||
|
|
|
||
|
|
kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
|
||
|
|
|
||
|
|
if (reg >= variant->num_registers) {
|
||
|
|
dev_warn(&hdmi->pdev->dev,
|
||
|
|
"Invalid register ID %u\n", reg);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
field = &variant->registers[reg];
|
||
|
|
base = __vc4_hdmi_get_field_base(hdmi, field->reg);
|
||
|
|
if (!base)
|
||
|
|
return;
|
||
|
|
|
||
|
|
writel(value, base + field->offset);
|
||
|
|
}
|
||
|
|
#define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val)
|
||
|
|
|
||
|
|
#endif /* _VC4_HDMI_REGS_H_ */
|